| Layout-aware pattern generation for maximizing supply noise effects on critical paths J Ma, J Lee, M Tehranipoor 2009 27th IEEE VLSI Test Symposium, 221-226, 2009 | 74 | 2009 |
| Layout-aware critical path delay test under maximum power supply noise effects J Ma, M Tehranipoor IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 34 | 2011 |
| A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications JX Ma, SW Sin, Seng-Pan U, RP Martins Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International …, 2006 | 22 | 2006 |
| Power-safe application of transition delay fault patterns considering current limit during wafer test W Zhao, J Ma, M Tehranipoor, S Chakravarty 2010 19th IEEE Asian Test Symposium, 301-306, 2010 | 17 | 2010 |
| Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG AC Junxia Ma, Jeremy Lee, Mohammad Tehranipoor IEEE International Workshop on Defect and Data Driven Test, 2008 | 17* | 2008 |
| Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes F Wu, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Virazel, J Ma, ... 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010 | 16 | 2010 |
| Silicon evaluation of faster than at-speed transition delay tests S Chakravarty, N Devta-Prasanna, A Gunda, J Ma, F Yang, H Guo, R Lai, ... 2012 IEEE 30th VLSI Test Symposium (VTS), 80-85, 2012 | 14 | 2012 |
| Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures J Ma, N Ahmed, M Tehranipoor 29th VLSI Test Symposium, 309-314, 2011 | 7 | 2011 |
| A novel method for fast identification of peak current during test W Zhao, S Chakravarty, J Ma, N Devta-Prasanna, F Yang, M Tehranipoor 2012 IEEE 30th VLSI Test Symposium (VTS), 191-196, 2012 | 5 | 2012 |
| Test pattern generation for open defects in power distribution networks JX Ma, J Lee, M Tehranipoor, A Crouch IEEE North Atlantic Test Workshop, 31-36, 2008 | 5 | 2008 |
| Power-safe application of TDF patterns to flip-chip designs during wafer test W Zhao, J Ma, M Tehranipoor, S Chakravarty ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (3 …, 2013 | 4 | 2013 |
| A layout-aware pattern grading procedure for critical paths considering power supply noise and crosstalk J Ma, M Tehranipoor, P Girard Journal of Electronic Testing 28 (2), 201-214, 2012 | 4 | 2012 |
| Background on VLSI Testing J Ma, M Tehranipoor Introduction to Hardware Security and Trust, 1-25, 2011 | 3 | 2011 |
| Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric J Ma, J Lee, M Tehranipoor, N Ahmed, P Girard Proceedings of the 20th symposium on Great lakes symposium on VLSI, 127-130, 2010 | 3 | 2010 |
| Layout-Aware Delay Fault Testing Techniques Considering Signal and Power Integrity Issues J Ma University of Connecticut, 2010 | 1 | 2010 |
| Implementing Hierarchical DFT Architecture for Ultra Large Designs Using DFTMAX Core Wrapping and Test Scheduling RRLSIC Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, ... SNUG Sillicon Valley 2014, 2014 | | 2014 |
| Extended Abstract: Developing a Novel Quality Metric for Path‐Delay Fault Pattern Evaluation JLMT Junxia Ma IEEE International Defect and Data Driven Testing (D3T) Workshop, 2009 | | 2009 |
| Layout‐Aware Pattern Generation for Critical Paths Considering Supply Voltage Noise MT Junxia Ma, Jeremy Lee SRC TECHCON, 2009 | | 2009 |
| Power Distribution Failure Analysis Using Transition-Delay Fault Patterns J Ma, J Lee, M Tehranipoor 2008 IEEE International Test Conference, 2008 | | 2008 |
| A 1.8-V 1.056-Gs/S 6-B Flash-Interpolation ADC For Mb-Ofdm Uwb Applications JX Ma, SW Sin, U Seng-Pan, RP Martins | | 2006 |