340mV-1.1 V, 289Gbps/W, 2090-gate NanoAES Hardware Accelerator with Area-optimized Encrypt/Decrypt GF (2 4) 2 Polynomials in 22nm tri-gate CMOS S Mathew, S Satpathy, V Suresh, H Kaul, M Anders, G Chen, A Agarwal, ...
IEEE Symposium on VLSI Circuits, 2014
168 2014 SK Mathew, D Johnston, S Satpathy, V Suresh, P Newman, MA Anders, ...
IEEE Journal of Solid-State Circuits 51 (7), 1695-1704, 2016
134 2016 μRNG: A 300-950mV 323Gbps/W all-digital full-entropy TRNG in 14nm FinFET CMOS S Mathew
IEEE Proc. of the ESSCIRC, 116-119, 2015
134 * 2015 A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS S Satpathy, SK Mathew, V Suresh, MA Anders, H Kaul, A Agarwal, ...
IEEE Journal of Solid-State Circuits 52 (4), 940-949, 2017
120 2017 An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS SK Satpathy, SK Mathew, R Kumar, V Suresh, MA Anders, H Kaul, ...
IEEE Journal of Solid-State Circuits 54 (4), 1074-1085, 2019
95 2019 Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing VB Suresh, WP Burleson
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (7), 1785-1793, 2015
58 2015 Entropy extraction in metastability-based TRNG VB Suresh, WP Burleson
Hardware-Oriented Security and Trust (HOST), 2010 IEEE International …, 2010
57 2010 Techniques for secure message authentication with unified hardware acceleration VB Suresh, KS Yap, SK Mathew, SK Satpathy
US Patent App. 15/393,196, 2018
39 2018 2.9 TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS M Anders, H Kaul, S Mathew, V Suresh, S Satpathy, A Agarwal, S Hsu, ...
2018 IEEE Symposium on VLSI Circuits, 39-40, 2018
36 2018 On-chip lightweight implementation of reduced NIST randomness test suite VB Suresh, D Antonioli, WP Burleson
2013 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2013
36 2013 Guarding machine learning hardware against physical side-channel attacks A Dubey, R Cammarota, V Suresh, A Aysu
ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (3), 1-31, 2022
35 2022 Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator V Suresh, S Mathew, S Satpathy
US Patent 10,928,847, 2021
33 2021 A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection V Suresh, R Kumar, M Anders, H Kaul, V De, S Mathew
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
32 2020 Energy-efficient bitcoin mining hardware accelerators VB Suresh, SK Satpathy, SK Mathew
US Patent 10,313,108, 2019
30 2019 Implementing hardware trojans: Experiences from a hardware trojan challenge GT Becker, A Lakshminarasimhan, L Lin, S Srivathsa, VB Suresh, ...
2011 IEEE 29th International Conference on Computer Design (ICCD), 301-304, 2011
28 2011 A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS R Kumar, X Liu, V Suresh, HK Krishnamurthy, S Satpathy, MA Anders, ...
IEEE Journal of Solid-State Circuits 56 (4), 1141-1151, 2021
27 2021 Non-linear physically unclonable function (PUF) circuit with machine-learning attack resistance VB Suresh, SK Mathew, SK Satpathy
US Patent 10,027,472, 2018
27 2018 Optimized SHA-256 datapath for energy-efficient high-performance Bitcoin mining VB Suresh, SK Satpathy, SK Mathew
US Patent 10,142,098, 2018
23 2018 Hardware apparatuses and methods for data decompression SK Satpathy, JD Guilford, SK Mathew, V Gopal, VB Suresh
US Patent App. 14/757,854, 2019
21 2019 Hardware apparatuses and methods for data decompression SK Satpathy, JD Guilford, SK Mathew, V Gopal, VB Suresh
US Patent 10,177,782, 2019
21 2019 
Sudhir SatpathyCompute Silicon Architect, Facebook Reality LabsAdresse e-mail validée de fb.com