Girish Pahwa

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Yogesh S. ChauhanFellow IEEE, FNAE, Professor-IIT KanpurAdresse e-mail validée de iitk.ac.in
chenming huUniversity of California, BerkeleyAdresse e-mail validée de eecs.berkeley.edu
Hussam AmrouchProfessor (W3) of AI Processor Design, Technical University of MunichAdresse e-mail validée de tum.de
Amit AgarwalP. K. Kelker Chair Professor, Indian Institute of Technology, Kanpur (India)Adresse e-mail validée de iitk.ac.in
Sayeef SalahuddinTSMC Distinguished Professor of EECS, University of California, BerkeleyAdresse e-mail validée de berkeley.edu
Tapas DuttaUniversity of GlasgowAdresse e-mail validée de glasgow.ac.uk
Amol GaidhaneMTS, GlobalFoundries || Post-Doc, Arizona State University || Ph.D., IIT KanpurAdresse e-mail validée de globalfoundries.com
Jörg HenkelProfessor of Computer Science, Karlsruhe Institute of TechnologyAdresse e-mail validée de kit.edu
Avirup DasguptaIndian Institute of Technology RoorkeeAdresse e-mail validée de ece.iitr.ac.in
SHIVENDRA SINGH PARIHARPostdoctoral Scholar, University of California Berkeley, CA, USAAdresse e-mail validée de berkeley.edu
Amit VermaDepartment of Electrical Engineering, Indian Institute of Technology KanpurAdresse e-mail validée de iitk.ac.in
Aniket GuptaUniversity of Notredame (Intern: KIT | IIT Roorkee | Daad Scholar, BTech: NIT Uttarakhand)Adresse e-mail validée de nd.edu
Florian KlemmeSiemens EDAAdresse e-mail validée de siemens.com
Chien-Ting TungUniversity of California, BerkeleyAdresse e-mail validée de berkeley.edu
sourabh khandelwalUC BerkeleyAdresse e-mail validée de berkeley.edu
Garima GillPhD, IIT JodhpurAdresse e-mail validée de iitj.ac.in
Sami SalaminPalestine Polytechnic UniversityAdresse e-mail validée de ppu.edu
Victor M. van SantenTechnical University of Munich (TUM)Adresse e-mail validée de tum.de
Anant SinghalPhD, Indian Institute of Technology JodhpurAdresse e-mail validée de iitj.ac.in
AYUSHI SHARMAIIT KanpurAdresse e-mail validée de iitk.ac.in

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Girish Pahwa

Assistant Professor, ICST, National Yang Ming Chiao Tung University

Adresse e-mail validée de nycu.edu.tw - Page d'accueil

Compact Modeling Negative Capacitance FET Cryogenic CMOS Ferroelectric Memories TFT


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Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance—Part II: Model validation G Pahwa, T Dutta, A Agarwal, S Khandelwal, S Salahuddin, C Hu, ... IEEE Transactions on Electron Devices 63 (12), 4986-4992, 2016	220	2016
Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance-Part I: Model Description G Pahwa, T Dutta, A Agarwal, S Khandelwal, S Salahuddin, C Hu, ... IEEE Transactions on Electron Devices 63 (12), 4981 - 4985, 2016	220	2016
Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Subthreshold Behavior G Pahwa, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 65 (11), 5130 - 5136, 2018	152	2018
Physical insights on negative capacitance transistors in nonhysteresis and hysteresis regimes: MFMIS versus MFIS structures G Pahwa, T Dutta, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 65 (3), 867-873, 2018	142	2018
Compact model for ferroelectric negative capacitance transistor with MFIS structure G Pahwa, T Dutta, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 64 (3), 1366-1374, 2017	117	2017
Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan IEEE Electron Device Letters 38 (8), 1161-1164, 2017	95	2017
Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance H Amrouch, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan IEEE Access 6, 52754-52765, 2018	87	2018
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach G Pahwa, T Dutta, A Agarwal, YS Chauhan European Solid-State Circuits Conference, 49-54, 2016	82	2016
Compact modeling of drain current, charges, and capacitances in long-channel gate-all-around negative capacitance MFIS transistor AD Gaidhane, G Pahwa, A Verma, YS Chauhan IEEE Transactions on Electron Devices 65 (5), 2024-2032, 2018	77	2018
Compact modeling of temperature effects in FDSOI and FinFET devices down to cryogenic temperatures G Pahwa, P Kushwaha, A Dasgupta, S Salahuddin, C Hu IEEE Transactions on Electron Devices 68 (9), 4223-4230, 2021	76	2021
Impact of variability on processor performance in negative capacitance finfet technology H Amrouch, G Pahwa, AD Gaidhane, CK Dabhi, F Klemme, O Prakash, ... IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 3127-3137, 2020	66	2020
Impact of process variations on negative capacitance FinFET devices and circuits T Dutta, G Pahwa, A Agarwal, YS Chauhan IEEE Electron Device Letters 39 (1), 147-150, 2017	56	2017
Numerical investigation of short-channel effects in negative capacitance MFIS and MFMIS transistors: Above-threshold behavior G Pahwa, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 66 (3), 1591-1598, 2019	49	2019
Impact of interface traps on negative capacitance transistor: Device and circuit reliability O Prakash, A Gupta, G Pahwa, J Henkel, YS Chauhan, H Amrouch IEEE Journal of the Electron Devices Society 8, 1193-1201, 2020	41	2020
Unveiling the impact of IR-drop on performance gain in NCFET-based processors H Amrouch, S Salamin, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan IEEE Transactions on Electron Devices 66 (7), 3215-3223, 2019	30	2019
Performance, power and cooling trade-offs with NCFET-based many-cores M Rapp, S Salamin, H Amrouch, G Pahwa, Y Chauhan, J Henkel Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019	29	2019
Gate-induced drain leakage in negative capacitance FinFETs AD Gaidhane, G Pahwa, A Verma, YS Chauhan IEEE Transactions on Electron Devices 67 (3), 802-809, 2020	26	2020
Impact of self-heating on negative-capacitance finfet: Device-circuit interaction O Prakash, G Pahwa, CK Dabhi, YS Chauhan, H Amrouch IEEE Transactions on Electron Devices 68 (4), 1420-1424, 2021	25	2021
A compact model of polycrystalline ferroelectric capacitor CT Tung, G Pahwa, S Salahuddin, C Hu IEEE Transactions on Electron Devices 68 (10), 5311-5314, 2021	23	2021
On the resiliency of NCFET circuits against voltage over-scaling G Paim, G Zervakis, G Pahwa, YS Chauhan, EAC da Costa, S Bampi, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (4), 1481-1492, 2021	21	2021

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