Border traps in Al2O3/In0. 53Ga0. 47As (100) gate stacks and their passivation by hydrogen anneals EJ Kim, L Wang, PM Asbeck, KC Saraswat, PC McIntyre
Applied Physics Letters 96 (1), 2010
227 2010 A Distributed Model for Border Traps in MOS Devices Y Yuan, L Wang, B Yu, B Shin, J Ahn, PC McIntyre, PM Asbeck, ...
IEEE Electron Device Letters 32 (4), 485-487, 2011
216 2011 Scaling of nanowire transistors B Yu, L Wang, Y Yuan, PM Asbeck, Y Taur
IEEE Transactions on Electron Devices 55 (11), 2846-2858, 2008
171 2008 Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications L Wang, E Yu, Y Taur, P Asbeck
IEEE Electron Device Letters 31 (5), 431-433, 2010
159 2010 Simulation of electron transport in high-mobility MOSFETs: Density of states bottleneck and source starvation MV Fischetti, L Wang, B Yu, C Sachs, PM Asbeck, Y Taur, M Rodwell
2007 IEEE International Electron Devices Meeting, 109-112, 2007
120 2007 Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE RegrowthU Singisetti, MA Wistey, GJ Burek, AK Baraskar, BJ Thibeault, ...
Electron Device Letters, IEEE 30 (11), 1128-1130, 2009
116 2009 A numerical Schrödinger–Poisson solver for radially symmetric nanowire core–shell structures L Wang, D Wang, PM Asbeck
Solid-state electronics 50 (11-12), 1732-1739, 2006
65 2006 Pragmatic design of nanoscale multi-gate CMOS JG Fossum, LQ Wang, JW Yang, SH Kim, VP Trivedi
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
60 2004 Nanowire photodetector and image sensor with internal gain D Wang, C Soci, Y Lo, A Zhang, D Aplin, L Wang, S Dayeh, XY Bao
US Patent 8,440,997, 2013
58 2013 III–V FET channel designs for high current densities and thin inversion layers M Rodwell, W Frensley, S Steiger, E Chagarov, S Lee, H Ryu, Y Tan, ...
68th Device Research Conference, 149-152, 2010
46 2010 Electrical Properties of Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs M Passlack, R Droopad, P Fejes, L Wang
IEEE electron device letters 30 (1), 2-4, 2008
42 2008 InGaN/GaN Schottky diodes with enhanced voltage handling capability for varactor applications W Lu, L Wang, S Gu, DPR Aplin, DM Estrada, KL Paul, PM Asbeck
IEEE electron device letters 31 (10), 1119-1121, 2010
35 2010 Analysis of reverse leakage current and breakdown voltage in GaN and InGaN/GaN Schottky barriers W Lu, L Wang, S Gu, DPR Aplin, DM Estrada, KL Paul, PM Asbeck
IEEE transactions on electron devices 58 (7), 1986-1994, 2011
31 2011 Self-consistent 1-D Schrödinger–Poisson solver for III–V heterostructures accounting for conduction band non-parabolicity L Wang, PM Asbeck, Y Taur
Solid-state electronics 54 (11), 1257-1262, 2010
22 2010 Low voltage transistors P Asbeck, L Wang
US Patent 8,148,718, 2012
17 2012 III-V MOSFETs: Scaling laws, scaling limits, fabrication processes MJW Rodwell, U Singisetti, M Wistey, GJ Burek, A Carter, A Baraskar, ...
2010 22nd International Conference on Indium Phosphide and Related Materials …, 2010
17 2010 IEDM Tech. Dig. MV Fischetti, L Wang, B Yu, C Sachs, PM Asbeck, Y Taur, M Rodwell
IEDM Tech. Dig, 109-112, 2007
14 2007 Trapped charge induced gate oxide breakdown A Neugroschel, L Wang, G Bersuker
Journal of applied physics 96 (6), 3388-3398, 2004
14 2004 Semiconductor devices with dopant migration suppression and method of fabrication thereof S Pradhan, D Zhao, L Wang, P Ranade, L Scudder
US Patent 9,112,057, 2015
10 2015 Analysis of photoelectronic response in semiconductor nanowires L Wang, P Asbeck
2006 Sixth IEEE Conference on Nanotechnology 2, 716-719, 2006
10 2006