| Posits: the good, the bad and the ugly F De Dinechin, L Forget, JM Muller, Y Uguen Proceedings of the Conference for Next Generation Arithmetic 2019, 1-10, 2019 | 128 | 2019 |
| Evaluating the hardware cost of the posit number system Y Uguen, L Forget, F De Dinechin 2019 29th International Conference on Field Programmable Logic and …, 2019 | 78 | 2019 |
| Design-space exploration for the Kulisch accumulator Y Uguen, F de Dinechin | 19 | 2017 |
| Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations Y Uguen, F de Dinechin, S Derrien 2017 27th International Conference on Field Programmable Logic and …, 2017 | 16 | 2017 |
| Application-specific arithmetic in high-level synthesis tools Y Uguen, FD Dinechin, V Lezaud, S Derrien ACM Transactions on Architecture and Code Optimization (TACO) 17 (1), 1-23, 2020 | 11 | 2020 |
| PyGA: a Python to FPGA compiler prototype Y Uguen, E Petit Proceedings of the 5th ACM SIGPLAN international workshop on artificial …, 2018 | 11 | 2018 |
| Comparing posit and IEEE-754 hardware cost L Forget, Y Uguen, F de Dinechin | 10 | 2021 |
| Hardware cost evaluation of the posit number system L Forget, Y Uguen, F De Dinechin Compas' 2019-Conférence d'informatique en Parallélisme, Architecture et …, 2019 | 9 | 2019 |
| A type-safe arbitrary precision arithmetic portability layer for HLS tools L Forget, Y Uguen, F de Dinechin, D Thomas Proceedings of the 10th International Symposium on Highly-Efficient …, 2019 | 6 | 2019 |
| High-level synthesis and arithmetic optimizations Y Uguen Université de Lyon, 2019 | 3 | 2019 |
| Exploration architecturale de l'accumulateur de Kulisch Y Uguen, F de Dinechin Compas' 2017-Conférence d’informatique en Parallélisme, Architecture et …, 2017 | 2 | 2017 |
| A high-level synthesis approach optimizing accumulations in floating-point programs using custom formats and operators Y Uguen, F de Dinechin, S Derrien 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 2 | 2017 |
| High-Level Synthesis Using Application-Specific Arithmetic: A Case Study Y Uguen, F de Dinechin, S Derrien | 1 | 2017 |
| SPU-sim : A cycle accurate simulator for the Stencil Processing Unit Y Uguen, S Rajopadhye http://perso.eleves.ens-rennes.fr/~yugue555/SPU-sim.pdf, 2015 | 1 | 2015 |
| High-level synthesis and arithmetic optimization applied to reductions Y Uguen, F de Dinechin, S Derrien http://perso.eleves.ens-rennes.fr/~yugue555/ArithHLS.pdf, 2016 | | 2016 |
| HAL Id: hal-01488916 Y Uguen, F De Dinechin | | |
| Master research Internship Y Uguen, F de Dinechin, S Derrien | | |
| Mise en oeuvre sur FPGA d’un processeur VLIW à l’aide d’outils de Synthèse de Haut-Niveau (Cairn Vex) Y Uguen | | |
