| Digital signal processing with field programmable gate arrays U Meyer-Baese Springer, 2007 | 1524 | 2007 |
| 数字信号处理的 FPGA 实现 U Meyer-Baese Qing hua da xue chu ban she, 2017 | 307* | 2017 |
| IPP@ HDL: Efficient intellectual property protection scheme for IP cores E Castillo, U Meyer-Baese, A Garcia, L Parrilla, A Lloris IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (5), 578-591, 2007 | 160 | 2007 |
| Robust bioinspired architecture for optical-flow computation G Botella, A García, M Rodríguez-Álvarez, E Ros, U Meyer-Baese, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (4), 616-629, 2009 | 103 | 2009 |
| Fast RNS FPL-based communications receiver design and implementation J Ramírez, A García, U Meyer-Baese, A Lloris International conference on field programmable logic and applications, 472-481, 2002 | 91 | 2002 |
| Implementation of a communications channelizer using FPGAs and RNS arithmetic U Meyer-Bäse, A García, F Taylor Journal of VLSI signal processing systems for signal, image and video …, 2001 | 64 | 2001 |
| Pipelined Hogenauer CIC filters using field-programmable logic and residue number system A Garcia, U Meyer-Baese, F Taylor Proceedings of the 1998 IEEE International Conference on Acoustics, Speech …, 1998 | 55 | 1998 |
| Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture G Botella, U Meyer-Baese, A García, M Rodríguez Digital Signal Processing 22 (6), 1174-1187, 2012 | 49 | 2012 |
| New power-of-2 RNS scaling scheme for cell-based IC design U Meyer-Base, T Stouraitis IEEE transactions on very large scale integration (VLSI) systems 11 (2), 280-283, 2003 | 46 | 2003 |
| Automated signature insertion in combinational logic patterns for HDL IP core protection E Castillo, L Parrilla, A Garcia, U Meyer-Baese, G Botella, A Lloris 2008 4th Southern Conference on Programmable Logic, 183-186, 2008 | 44 | 2008 |
| A comparison of pipelined RAG-n and DA FPGA-based multiplierless filters U Meyer-Baese, J Chen, CH Chang, AG Dempster APCCAS 2006-2006 IEEE Asia Pacific Conference on Circuits and Systems, 1555-1558, 2006 | 42 | 2006 |
| Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm U Meyer-Baese, G Botella, DET Romero, M Kumm Independent Component Analyses, Compressive Sampling, Wavelets, Neural Net …, 2012 | 41 | 2012 |
| RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic A Garcia, U Meyer-Base, A Lloris, FJ Taylor 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 486-489, 1999 | 41 | 1999 |
| Multiple constant multiplication with ternary adders M Kumm, M Hardieck, J Willkomm, P Zipf, U Meyer-Baese 2013 23rd International Conference on Field programmable Logic and …, 2013 | 38 | 2013 |
| Design and implementation of high-performance RNS wavelet processors using custom IC technologies J Ramírez, U Meyer-Bäse, F Taylor, A García, A Lloris Journal of VLSI signal processing systems for signal, image and video …, 2003 | 37 | 2003 |
| A parallel CORDIC architecture dedicated to compute the Gaussian potential function in neural networks A Meyer-Bäse, R Watzel, U Meyer-Bäse, S Foo Engineering Applications of Artificial Intelligence 16 (7-8), 595-605, 2003 | 36 | 2003 |
| High performance, reduced complexity programmable RNS-FPL merged FIR filters J Ramirez, U Meyer-Baese Electronics Letters 38 (4), 1, 2002 | 36 | 2002 |
| A low cost matching motion estimation sensor based on the NIOS II microprocessor D González, G Botella, U Meyer-Baese, C García, C Sanz, ... Sensors 12 (10), 13126-13149, 2012 | 35 | 2012 |
| FPGA-based multimodal embedded sensor system integrating low-and mid-level vision G Botella, JA Martín H, M Santos, U Meyer-Baese Sensors 11 (8), 8164-8179, 2011 | 35 | 2011 |
| Discrete wavelet transform FPGA design using MatLab/Simulink U Meyer-Baese, A Vera, A Meyer-Baese, M Pattichis, R Perry Independent Component Analyses, Wavelets, Unsupervised Smart Sensors, and …, 2006 | 35 | 2006 |
Antonio GarcíaFull Professor, Dept. Electronics and Computer Technology, University of GranadaAdresse e-mail validée de ugr.es