| Programmable packet scheduling at line rate A Sivaraman, S Subramanian, M Alizadeh, S Chole, ST Chuang, ... Proceedings of the 2016 ACM SIGCOMM Conference, 44-57, 2016 | 353 | 2016 |
| drmt: Disaggregated programmable switching S Chole, A Fingerhut, S Ma, A Sivaraman, S Vargaftik, A Berger, ... Proceedings of the Conference of the ACM Special Interest Group on Data …, 2017 | 202 | 2017 |
| Towards programmable packet scheduling A Sivaraman, S Subramanian, A Agrawal, S Chole, ST Chuang, T Edsall, ... Proceedings of the 14th ACM workshop on hot topics in networks, 1-7, 2015 | 77 | 2015 |
| Methods and Apparatus for Constructing Digital Circuits for Performing Matrix Operations SCH Ma, ST Chuang, SV Chole US Patent App. 16/377,103, 2020 | 7 | 2020 |
| Method and apparatus for efficiently processing convolution neural network operations ST Chuang, SV Chole, SCH Ma US Patent 11,151,416, 2021 | 6 | 2021 |
| Method And Apparatus For Scheduling Matrix Operations In Digital Processing Systems S Chuang, SV Chole, SC Ma US Patent App. 16/869,520, 2020 | 4 | 2020 |
| SparseCore: An accelerator for structurally sparse CNNs S Chole, R Tadishetti, S Reddy Proc. SysML Conf, 1-3, 2018 | 4 | 2018 |
| Methods and Apparatus For Packet Reorder Flow in a Neural Network Processing System R Tadishetti, S Twu, A Chang, SV Chole US Patent App. 18/737,585, 2024 | 1 | 2024 |
| Methods and apparatus for accessing external memory in a neural network processing system S Ma, ST Chuang, S Chole US Patent 12,008,463, 2024 | 1 | 2024 |
| Grid Sampling Methodologies in Neural Network Processor Systems J Xue, S Ma, S Chuang, S Chole US Patent App. 18/452,022, 2025 | | 2025 |
| Systems and Processes for Data Reshape and Transport Using Matrix Processor Circuits R Tadishetti, VV Kamat, SV Chole, S Chuang, SC Ma US Patent App. 18/930,861, 2025 | | 2025 |
| MACHINE LEARNING MODEL SCALABILITY WITH DISTRIBUTED MULTI-LAYER PROCESSING S Chuang, SC Ma, SV Chole, C Calamvokis US Patent App. 18/789,431, 2025 | | 2025 |
| Methods and Apparatus For Recomputing Neural Networks R Tadishetti, SV Chole, S Chuang, SC Ma US Patent App. 18/768,801, 2025 | | 2025 |
| Methods and Devices for Clock Forwarding and Realignment SCH Ma, ST Chuang, SV Chole US Patent App. 18/759,650, 2025 | | 2025 |
| Feature extraction with a convolutional neural network ST Chuang, SV Chole, SCH Ma US Patent 12,182,717, 2024 | | 2024 |
| Methods And Apparatus For Managing Weight Data Accesses For Neural Network Processors SV Chole, ST Chuang, SCH Ma US Patent App. 18/212,618, 2024 | | 2024 |
| Methods And Apparatus For Matrix Processing In A Neural Network Processing System SV Chole, ST Chuang, SCH Ma US Patent App. 18/212,648, 2024 | | 2024 |
| Power-Efficient Clocking and Clock Shaping S Chole, ST Chuang, S Ma, P Sarrazin US Patent App. 18/315,074, 2024 | | 2024 |
| Systems and processes for organizing and controlling multiple matrix processor circuits SCH Ma, ST Chuang, SV Chole US Patent 12,141,226, 2024 | | 2024 |
| Digital Processing Circuits and Methods of Matrix Operations in an Artificially Intelligent Environment SV Chole, ST Chuang, SCH Ma US Patent App. 18/638,512, 2024 | | 2024 |
