| Matraptor: A sparse-sparse matrix multiplication accelerator based on row-wise product N Srivastava, H Jin, J Liu, D Albonesi, Z Zhang 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 236 | 2020 |
| Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ... Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 163 | 2018 |
| Tensaurus: A versatile accelerator for mixed sparse-dense tensor computations N Srivastava, H Jin, S Smith, H Rong, D Albonesi, Z Zhang 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 132 | 2020 |
| Designing secure cryptographic accelerators with information flow enforcement: A case study on aes Z Jiang, H Jin, GE Suh, Z Zhang Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 19 | 2019 |
| Stainless steel fiber felt as the anode diffusion backing and current collector for μ-DMFC R Xue, S Sang, H Jin, Q Shen, Y Zhang, X Liu, X Zhang Microelectronic engineering 119, 159-163, 2014 | 10 | 2014 |
| Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software-Programmable FPGAs. Int’l Symp. on Field-Programmable Gate Arrays (FPGA)(Feb 2018) Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ... doi. org/10.1145/3174243.3174255, 2018 | 5 | 2018 |
| Digital Scope Implemented on Altera DE1-SoC H Jin Cornell University, School of Electrical and Computer Engineering, MEng …, 2016 | 2 | 2016 |
| Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns H Jin, Z Yue, Z Zhao, Y Du, C Deng, N Srivastava, Z Zhang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
