Követés
Dr. Hitesh pahuja
Dr. Hitesh pahuja
C-DAC Ministry of Electronics & Information Technology
E-mail megerősítve itt: cdac.in
Cím
Hivatkozott rá
Hivatkozott rá
Év
Low power FinFET based 10T SRAM cell
N Kaur, N Gupta, H Pahuja, B Singh, S Panday
2016 Second International Innovative Applications of Computational …, 2016
172016
Real time monitoring & alert system for landslide
S Kapoor, H Pahuja, B Singh
2016 2nd International Conference on Contemporary Computing and Informatics …, 2016
152016
Design and comparative analysis of low power 64 Bit SRAM and its peripherals using power reduction techniques
G Vashisht, H Pahuja, B Singh, S Panday
2016 5th International Conference on Wireless Networks and Embedded Systems …, 2016
82016
Design and Performance analysis of CMOS based D Flip-Flop using Low power Techniques
A Saxena, M Kaur, H Pahuja, VA Chhabra
International Journal of Research in Electronics and Computer Engineering 4 (5), 2017
72017
A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations
H Pahuja, M Tyagi, S Panday, B Singh
Integration 60, 99-116, 2018
62018
A novel design of low power nonvolatile 10T1R SRAM cell
N Gupta, H Pahuja, B Singh, N Nagpal
2016 5th International Conference on Wireless Networks and Embedded Systems …, 2016
42016
Design and performance analysis of operational transconductance amplifier using FinFET
A Kumari, B Singh, H Pahuja, SG Jambagi, VA Chhabra
2018 8th International Conference on Cloud Computing, Data Science …, 2018
32018
Design of SRAM array using Reversible logic for an efficient SoC design
C Sharma, V Chhabra, B Singh, H Pahuja
2017 International Conference on Inventive Computing and Informatics (ICICI …, 2017
32017
Design and Analysis of Low Power Universal Line Encoder & Decoder
A Taya, B Singh, H Pahuja
Microelectronics and Solid State Electronics Journal 5 (1), 7-13, 2016
32016
LEAKAGE IMMUNE SINGLE ENDED 8T SRAM CELL FOR ULTRA-LOW POWER MEMORY DESIGN
H PAHUJA, M TYAGI, B SINGH, S PANDAY
Journal of Engineering Science and Technology 14 (2), 629-628, 2019
22019
Design and analysis of priority encoder with low power MTCMOS technique
S Saini, B Singh, H Pahuja, VA Chhabra
2018 8th International Conference on Cloud Computing, Data Science …, 2018
22018
Study of reversible logic synthesis with application in SOC: A review
C Sharma, H Pahuja, M Dadhwal, B Singh
IOP Conference Series: Materials Science and Engineering 225 (1), 012250, 2017
22017
Design and analysis of the high speed AES using ancient Vedic mathematics novel approach
A Kumar, H Pahuja, B Singh
2016 5th International Conference on Wireless Networks and Embedded Systems …, 2016
22016
Development of Real Time Helmet based Authentication with Smart Dashboard for Two Wheelers
AK Pardeshi, H Pahuja, B Singh
The International Symposium on Intelligent Systems Technologies and …, 2016
22016
A 16 nm robust DG-FinFET based 10T static random-access memory cell design for ultra-low power memory design
H Pahuja, M Tyagi, S Panday, B Singh
Advanced Science, Engineering and Medicine 9 (12), 1022-1028, 2017
12017
Design and analysis of single-ended robust low power 8T SRAM cell
N Gupta, H Pahuja
MATEC Web of Conferences 57, 01005, 2016
12016
Industry
H Pahuja, PK Khosla, B Singh
Advances in Nonconventional Machining Processes, 133, 2020
2020
Artificial Intelligence and Robotics in The Manufacturing Industry: Opportunities and Challenges
H Pahuja, PK Khosla, B Singh
Advances in Nonconventional Machining Processes, 133-147, 2020
2020
Designing of a Gender Based Classifier for Western Music
A Tasleem, S Singh, B Singh, H Pahuja
International Conference on Advances in Computing and Data Sciences, 81-90, 2016
2016
Design and Analysis of Faster Multiplier using Vedic Mathematics Technique
C Mohali
International Journal of Computer Applications 975, 8887, 0
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Cikkek 1–20