A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC JK Sahani, A Singh, A Agarwal
AEU-International Journal of Electronics and Communications 124, 153344, 2020
20 2020 A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 JK Sahani, A Singh, A Agarwal
Journal of Circuits, Systems and Computers 29 (09), 2050142, 2020
11 2020 Design of full adder circuit using double gate MOSFET JK Sahani, S Singh
2015 Fifth International Conference on Advanced Computing & Communication …, 2015
10 2015 Design of operational transconductance amplifier using double gate MOSFET JK Sahani, S Suman, PK Ghosh, S Lakshmangarh
Innovative Syst. Des. Eng. IISTE 5, 42-56, 2014
6 2014 A 2.3 mW Multi-Frequency Clock Generator with JK Sahani, A Singh, A Agarwal
Journal of Circuits, Systems and Computers 29 (08), 2050130, 2020
5 2020 A high resolution and low jitter 5-bit flash TDC architecture for high speed intelligent systems JK Sahani, A Singh, A Agarwal
Intelligent Systems and Applications: Proceedings of the 2019 Intelligent …, 2020
5 2020 A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS JK Sahani, A Singh, A Agarwal
Circuits, Systems, and Signal Processing 41 (3), 1299-1323, 2022
3 2022 A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator JK Sahani, A Singh, A Agarwal
International Journal of Circuit Theory and Applications 50 (8), 2900-2912, 2022
1 2022 Implementation of Full Adder Circuit using Stack Technique JK Sahani
Computer Engineering and Intelligent Systems 6 (11), 22-32, 2015
1 2015 A Low Jitter and High-Speed Flash TDC with PVT Calibration and Its Testing Methodology JK Sahani, A Singh, A Agarwal
International Symposium on VLSI Design and Test, 95-108, 2023
2023 A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed JK Sahani, A Singh, A Agarwal
Intelligent Systems and Applications: Proceedings of the 2019 Intelligent …, 2019
2019 Double Gate based Wide Bandwidth and high gain Operational Transconductance Amplifier JK Sahani, PK Ghosh, S Suman
Design of Second Order Low Pass and High Pass Filter using Double Gate MOSFET based OTA JK Sahani, S Suman, PK Ghosh, S Lakshmangarh
Dr. Shruti SumanAssociate Professor, P P Savani University, Surat, Gujrat, Previous: K L University, Andhra PradeshE-mail megerősítve itt: ppsu.ac.in