| An 8 Bit 4 GS/s 120 mW CMOS ADC H Wei, P Zhang, BD Sahoo, B Razavi Solid-State Circuits, IEEE Journal of 49 (8), 1751-1761, 2014 | 180 | 2014 |
| An 8 Bit 4 GS/s 120 mW CMOS ADC BR H Wei, P Zhang, BD Sahoo Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 180* | 2013 |
| An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC H Wei, CH Chan, UF Chio, SW Sin, U Seng-Pan, RP Martins, F Maloberti IEEE Journal of Solid-State Circuits 47 (11), 2763-2772, 2012 | 122 | 2012 |
| A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS H Wei, CH Chan, UF Chio, SW Sin, U Seng-Pan, R Martins, F Maloberti Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 …, 2011 | 99 | 2011 |
| Enhanced hydrogen generation by hydrolysis of Mg doped with flower-like MoS2 for fuel cell applications M Huang, L Ouyang, J Liu, H Wang, H Shao, M Zhu Journal of Power Sources 365, 273-281, 2017 | 92 | 2017 |
| A 1.6-GS/s 12.2-mW seven-/eight-way split time-interleaved SAR ADC achieving 54.2-dB SNDR with digital background timing mismatch calibration M Guo, J Mao, SW Sin, H Wei, RP Martins IEEE Journal of Solid-State Circuits 55 (3), 693-705, 2019 | 75 | 2019 |
| Design and experimental verification of a power effective flash-SAR subranging ADC UF Chio, HG Wei, Y Zhu, SW Sin, U Seng-Pan, RP Martins, F Maloberti IEEE Transactions on Circuits and Systems II: Express Briefs 57 (8), 607-611, 2010 | 57 | 2010 |
| Linearity analysis on a series‐split capacitor array for high‐speed SAR ADCs Y Zhu, UF Chio, HG Wei, SW Sin, SP U, RP Martins VLSI Design 2010 (1), 706548, 2010 | 43 | 2010 |
| A power-efficient capacitor structure for high-speed charge recycling SAR ADCs Y Zhu, UF Chio, HG Wei, SW Sin, U Seng-Pan, RP Martins 2008 15th IEEE International Conference on Electronics, Circuits and Systems …, 2008 | 38 | 2008 |
| A 5 GS/s 29 mW interleaved SAR ADC with 48.5 dB SNDR using digital-mixing background timing-skew calibration for direct sampling applications M Guo, J Mao, SW Sin, H Wei, RP Martins IEEE Access 8, 138944-138954, 2020 | 37 | 2020 |
| A 29mw 5gs/s time-interleaved sar adc achieving 48.5 db sndr with fully-digital timing-skew calibration based on digital-mixing M Guo, J Mao, SW Sin, H Wei, RP Martins 2019 Symposium on VLSI Circuits, C76-C77, 2019 | 32 | 2019 |
| A rapid power-switchable track-and-hold amplifier in 90-nm CMOS HG Wei, UF Chio, Y Zhu, SW Sin, U Seng-Pan, RP Martins IEEE Transactions on Circuits and Systems II: Express Briefs 57 (1), 16-20, 2010 | 26 | 2010 |
| A Power Scalable 6-bit 1.2 GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier HG Wei, UF Chio, Y Zhu, SW Sin, U Seng-Pan, RP Martins 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 5-8, 2008 | 20 | 2008 |
| A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application RPM Zhijie Chen, Yang Jiang, Chenyan Cai, Hegong Wei IEEE Asian Solid-State Circuit Conference, 2012 | 13* | 2012 |
| An 11b 60MS/s 2.1 mW two-step time-interleaved SAR-ADC with reused S&H SW Sin, L Ding, Y Zhu, HG Wei, CH Chan, UF Chio, U Seng-Pan, ... 2010 Proceedings of ESSCIRC, 218-221, 2010 | 13 | 2010 |
| A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs UF Chio, HG Wei, Y Zhu, SW Sin, U Seng-Pan, RP Martins APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 1164-1167, 2008 | 12 | 2008 |
| A 10b 1.6 GS/s 12.2 mW 7/8-way split time-interleaved SAR ADC with digital background mismatch calibration M Guo, J Mao, SW Sin, H Wei, RP Martins 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 11 | 2019 |
| On-chip small capacitor mismatches measurement technique using beta-multiplier-biased ring oscillator SW Sin, HG Wei, UF Chio, Y Zhu, U Seng-Pan, RP Martins, F Maloberti 2009 IEEE Asian Solid-State Circuits Conference, 49-52, 2009 | 10 | 2009 |
| Seng-Pan U, and RP Martins,“ Y Zhu, UF Chio, HG Wei, SW Sin A power-efficient capacitor structure for high-speed charge recycling SAR …, 2008 | 9 | 2008 |
| Cascade analog-to-digital converting system HG Wei, Y Zhu, SW Sin, U Seng-Pan, RP da Silva Martins, F Maloberti US Patent 8,466,823, 2013 | 8 | 2013 |