| Impact of temperature on analog/RF, linearity and reliability performance metrics of tunnel FET with ultra-thin source region P Singh, DS Yadav Applied physics A 127 (9), 671, 2021 | 28 | 2021 |
| Design and investigation of f-shaped tunnel fet with enhanced analog/rf parameters P Singh, DS Yadav Silicon, 1-16, 2021 | 21 | 2021 |
| Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET P Singh, DS Yadav Current Applied Physics 44, 90-101, 2022 | 18 | 2022 |
| Impactful study of f-shaped tunnel fet P Singh, DS Yadav Silicon 14 (10), 5359-5365, 2022 | 17 | 2022 |
| Spectroscopic and simulation analysis of facile PEDOT: PSS layer deposition-silicon for perovskite solar cell P Singh, A Raman, N Kumar Silicon 12 (8), 1769-1777, 2020 | 15 | 2020 |
| Performance analysis of ITCs on analog/RF, linearity and reliability performance metrics of tunnel FET with ultra-thin source region P Singh, DS Yadav Applied Physics A 128 (7), 612, 2022 | 11 | 2022 |
| Temperature impact on linearity and analog/rf performance metrics of a novel charge plasma tunnel fet N Parmar, P Singh, DP Samajdar, DS Yadav Applied Physics A 127 (4), 266, 2021 | 9 | 2021 |
| Assessing the Impact of Drain Underlap Perspective Approach to Investigate DC/RF to Linearity Behavior of L-Shaped TFET P Singh, DS Yadav Silicon 14 (17), 11471-11481, 2022 | 8 | 2022 |
| Design and investigation of junction-less TFET (JL-TFET) for the realization of logic gates B Shah, P Singh, A Raman, NP Singh Nano, 2450160, 2024 | 5 | 2024 |
| Ultra thin finger-like source region-based TFET: Temperature sensor P Singh, A Raman, DS Yadav, N Kumar, A Dixit, MDHR Ansari IEEE Sensors Letters, 2024 | 4 | 2024 |
| Implementation of Logic Gates Using Drain Engineering Dual Metal Gate-Based Charge Plasma TFET (DE-DMG-CP-TFET) N Mahoviya, P Singh, DS Yadav Nano 18 (12), 2350081, 2023 | 3 | 2023 |
| Analog and linearity performance analysis of ferroelectric vertical tunnel field effect transistor with and without source pocket AK Singh, R Kumar, H Maity, P Singh, S Singh International Journal of Numerical Modelling: Electronic Networks, Devices …, 2024 | 1 | 2024 |
| Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application P Singh, DS Yadav Engineering Research Express 6 (1), 015319, 2024 | 1 | 2024 |
| Effect of SiGe-Composite Placement on Quantum Effects of a Nanowire FET Using NEGF A Raman, R Sachdeva, P Kumar, P Singh Silicon 17 (2), 259-266, 2025 | | 2025 |
| Assessing the Impact of Source Pocket Length Variation to Examine DC/RF to Linearity Performance of DG-TFET DS Yadav, P Singh, P Roat Nano 18 (04), 2350027, 2023 | | 2023 |
Dr. Dharmendra Singh YadavDepartment of Electronics and Communication Engineering, NIT Kurukshetra, Haryana, INDIAE-mail megerősítve itt: nitkkr.ac.in