| Scaling, power, and the future of CMOS M Horowitz, E Alon, D Patil, S Naffziger, R Kumar, K Bernstein IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 7 …, 2005 | 481 | 2005 |
| The implementation of the Itanium 2 microprocessor SD Naffziger, G Colon-Bonet, T Fischer, R Riedlinger, TJ Sullivan, ... IEEE Journal of Solid-State Circuits 37 (11), 1448-1460, 2002 | 295 | 2002 |
| The implementation of a 2-core, multi-threaded Itanium family processor S Naffziger, B Stackhouse, T Grutkowski, D Josephson, J Desai, E Alon, ... IEEE Journal of Solid-state circuits 41 (1), 197-209, 2005 | 285 | 2005 |
| Power and temperature control on a 90-nm Itanium family processor R McGowen, CA Poirier, C Bostak, J Ignowski, M Millican, WH Parks, ... IEEE Journal of Solid-State Circuits 41 (1), 229-237, 2005 | 279 | 2005 |
| A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency HP Le, M Seeman, SR Sanders, V Sathe, S Naffziger, E Alon 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 210-211, 2010 | 238 | 2010 |
| Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation T Chen, S Naffziger IEEE transactions on very large scale integration (VLSI) systems 11 (5), 888-899, 2003 | 229 | 2003 |
| Pioneering chiplet technology and design for the amd epyc™ and ryzen™ processor families: Industrial product S Naffziger, N Beck, T Burd, K Lepak, GH Loh, M Subramony, S White 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 197 | 2021 |
| A 90-nm variable frequency clock system for a power-managed itanium architecture processor T Fischer, J Desai, B Doyle, S Naffziger, B Patella IEEE journal of solid-state circuits 41 (1), 218-228, 2005 | 172 | 2005 |
| Power and temperature control on a 90nm Itanium/sup/spl reg//-family processor C Poirier, R McGowen, C Bostak, S Naffziger ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 145 | 2005 |
| 2.2 AMD chiplet architecture for high-performance server and desktop products S Naffziger, K Lepak, M Paraschou, M Subramony 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 44-45, 2020 | 140 | 2020 |
| A sub-nanosecond 0.5/spl mu/m 64 b adder design S Naffziger 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical …, 1996 | 126 | 1996 |
| Method and apparatus for thermal control of processing nodes A Branover, SD Naffziger US Patent 8,793,512, 2014 | 106 | 2014 |
| ‘Zeppelin’: An SoC for multichip architectures N Beck, S White, M Paraschou, S Naffziger 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 40-42, 2018 | 102 | 2018 |
| Voltage droop mitigation through instruction issue throttling SD Naffziger, MG Butler US Patent 7,937,563, 2011 | 93 | 2011 |
| Resonant-clock design for a power-efficient, high-volume x86-64 microprocessor VS Sathe, S Arekapudi, A Ishii, C Ouyang, MC Papaefthymiou, S Naffziger IEEE Journal of Solid-State Circuits 48 (1), 140-149, 2012 | 92 | 2012 |
| 5.6 adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor A Grenat, S Pant, R Rachala, S Naffziger 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 88 | 2014 |
| System, method and apparatus for conserving power consumed by a system having a processor integrated circuit DC Soltis Jr, S Naffziger US Patent 7,028,196, 2006 | 84 | 2006 |
| Adapting VLSI clocking to short term voltage transients S Naffziger, ES Fetzer US Patent 6,586,971, 2003 | 84 | 2003 |
| Method and apparatus for conserving power on a multiprocessor integrated circuit D Knee, S Naffziger US Patent 6,922,783, 2005 | 78 | 2005 |
| Mechanism for controlling power consumption in a processing node SD Naffziger US Patent 8,495,395, 2013 | 73 | 2013 |