| Rate analysis for embedded systems A Mathur, A Dasdan, RK Gupta ACM Transactions on Design Automation of Electronic Systems (TODAES) 3 (3 …, 1998 | 74 | 1998 |
| Circuit comparison by information loss matching A Mathur, D Goyal US Patent 7,222,317, 2007 | 45 | 2007 |
| Functional equivalence verification tools in high-level synthesis flows A Mathur, M Fujita, E Clarke, P Urard IEEE Design & Test of Computers 26 (4), 88-95, 2009 | 41 | 2009 |
| Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision S Saluja, A Mathur US Patent 6,772,399, 2004 | 39 | 2004 |
| Non-cycle-accurate sequential equivalence checking P Chauhan, D Goyal, G Hasteer, A Mathur, N Sharma Proceedings of the 46th Annual Design Automation Conference, 460-465, 2009 | 38 | 2009 |
| Embedded tutorial: Formal equivalence checking between system-level models and RTL A Koelbl, Y Lu, A Mathur ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 36 | 2005 |
| Timing driven placement reconfiguration for fault tolerance and yield enhancement in FPGAs A Mathur, CL Liu Proceedings ED&TC European Design and Test Conference, 165-169, 1996 | 34 | 1996 |
| Procedure for optimizing mergeability and datapath widths of data flow graphs S Saluja, A Mathur US Patent 6,807,651, 2004 | 31 | 2004 |
| Power reduction techniques and flows at RTL and system level A Mathur, Q Wang 2009 22nd International Conference on VLSI Design, 28-29, 2009 | 23 | 2009 |
| Improved merging of datapath operators using information content and required precision analysis A Mathur, S Saluja Proceedings of the 38th annual Design Automation Conference, 462-467, 2001 | 22 | 2001 |
| System, method and computer program product for equivalence checking between designs with sequential differences A Mathur, N Sharma, D Goyal, G Hasteer, R Mukherjee US Patent 7,350,168, 2008 | 15 | 2008 |
| RATAN: A tool for rate analysis and rate constraint debugging for embedded systems A Dasdan, A Mathur, RK Gupta Proceedings European Design and Test Conference. ED & TC 97, 2-6, 1997 | 15 | 1997 |
| Compression-relaxation: a new approach to performance driven placement for regular architectures A Mathur, CL Liu Proceedings of the 1994 IEEE/ACM international conference on Computer-aided …, 1994 | 15 | 1994 |
| Design for Verification in System-level Models and RTL A Mathur, V Krishnaswamy Proceedings of the 44th annual Design Automation Conference, 193-198, 2007 | 13 | 2007 |
| Efficient equivalence checking of multi-phase designs using retiming G Hasteer, A Mathur, P Banerjee Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 13 | 1998 |
| Re-engineering of timing constrained placements for regular architectures A Mathur, KC Chen, CL Liu Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 13 | 1995 |
| Low-power design using the Si2 common power format S Carver, A Mathur, L Sharma, P Subbarao, S Urish, Q Wang IEEE Design & Test of Computers 29 (2), 62-70, 2012 | 12 | 2012 |
| Generalized Kraft’s Inequality and Discrete k-Modal Search A Mathur, EM Reingold SIAM Journal on Computing 25 (2), 420-447, 1996 | 11 | 1996 |
| Integrated circuit design system, method, and computer program product that takes into account observability based clock gating conditions V Ramachandran, N Tripathi, A Mathur, S Roy, M Haldar US Patent 7,761,827, 2010 | 10 | 2010 |
| Reducing datapath widths by rebalancing data flow topology S Saluja, A Mathur US Patent 6,832,357, 2004 | 10 | 2004 |
