| Modeling and minimization of PMOS NBTI effect for robust nanometer design R Vattikonda, W Wang, Y Cao Proceedings of the 43rd annual Design Automation Conference, 1047-1052, 2006 | 627 | 2006 |
| Predictive modeling of the NBTI effect for reliable design S Bhardwaj, W Wang, R Vattikonda, Y Cao, S Vrudhula IEEE Custom Integrated Circuits Conference 2006, 189-192, 2006 | 541 | 2006 |
| Compact modeling and simulation of circuit reliability for 65-nm CMOS technology W Wang, V Reddy, AT Krishnan, R Vattikonda, S Krishnan, Y Cao IEEE Transactions on Device and Materials Reliability 7 (4), 509-517, 2007 | 470 | 2007 |
| The impact of NBTI on the performance of combinational and sequential circuits W Wang, S Yang, S Bhardwaj, R Vattikonda, S Vrudhula, F Liu, Y Cao Proceedings of the 44th annual Design Automation Conference, 364-369, 2007 | 296 | 2007 |
| Write driver for write assistance in memory device CH Jung, N Desai, R Vattikonda US Patent 9,030,893, 2015 | 60 | 2015 |
| Wide range multiport bitcell CH Jung, R Vattikonda, N Desai, SS Yoon US Patent 8,971,096, 2015 | 39 | 2015 |
| Scalable model for predicting the effect of negative bias temperature instability for reliable design S Bhardwaj, W Wang, R Vattikonda, Y Cao, S Vrudhula IET circuits, devices & systems 2 (4), 361-371, 2008 | 37 | 2008 |
| An integrated modeling paradigm of circuit reliability for 65nm cmos technology W Wang, V Reddy, AT Krishnan, R Vattikonda, S Krishnan, Y Cao 2007 IEEE Custom Integrated Circuits Conference, 511-514, 2007 | 35 | 2007 |
| Memory with a sleep mode CH Jung, R Vattikonda, TCY Kwok US Patent App. 14/261,192, 2015 | 27 | 2015 |
| Hybrid ternary content addressable memory R Vattikonda, N Desai, CH Jung, SS Yoon, E Terzioglu US Patent 8,934,278, 2015 | 27 | 2015 |
| Static NAND cell for ternary content addressable memory (TCAM) E Terzioglu, N Desai, R Vattikonda, CH Jung, SS Yoon US Patent 8,958,226, 2015 | 22 | 2015 |
| Apparatus and method for writing data to memory array circuits C Jung, CH Jung, SS Yoon, R Vattikonda, N Desai US Patent 9,536,578, 2017 | 18 | 2017 |
| A new simulation method for nbti analysis in spice environment R Vattikonda, Y Luo, A Gyure, X Qi, S Lo, M Shahram, Y Cao, K Singhal, ... 8th International Symposium on Quality Electronic Design (ISQED'07), 41-46, 2007 | 18 | 2007 |
| Wide-range level-shifter CH Jung, F Guo, R Vattikonda US Patent 9,432,022, 2016 | 13 | 2016 |
| High-speed memory write driver circuit with voltage level shifting features N Desai, R Vattikonda, CH Jung US Patent 8,976,607, 2015 | 10 | 2015 |
| Pulse generation in dual supply systems CH Jung, N Desai, R Vattikonda US Patent 9,154,117, 2015 | 8 | 2015 |
| Pseudo-NOR cell for ternary content addressable memory R Vattikonda, N Desai, CH Jung US Patent 8,891,273, 2014 | 8 | 2014 |
| High speed voltage level shifter V Narayanan, R Vattikonda, D Lu, R Vilangudipitchai, S Sinharoy, R Chen US Patent 9,948,303, 2018 | 6 | 2018 |
| SRAM cell optimization for ultra-low power standby H Qin, R Vattikonda, T Trinh, Y Cao, J Rabaey Journal of Low Power Electronics 2 (3), 401-411, 2006 | 6 | 2006 |
| Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors R Ramaraju, R Vattikonda, S Sinharoy, D Lu, P Bo US Patent 10,164,768, 2018 | 4 | 2018 |
Yu CaoProfessor, University of MinnesotaEmail yang diverifikasi di umn.edu