| Method and system for packet classification with reduced memory space and enhanced access speed SH Cho, SD Wang US Patent 7,953,082, 2011 | 32 | 2011 |
| Swarm model checking on the GPU R DeFrancisco, S Cho, M Ferdman, SA Smolka International Journal on Software Tools for Technology Transfer 22 (5), 583-599, 2020 | 29 | 2020 |
| Taming the killer microsecond S Cho, A Suresh, T Palit, M Ferdman, N Honarmand 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 24 | 2018 |
| Flick: Fast and Lightweight ISA-Crossing Call for Heterogeneous-ISA Environments S Cho, H Chen, S Madaminov, M Ferdman, P Milder 47th IEEE/ACM International Symposium on Computer Architecture, 2020 | 10 | 2020 |
| FPGASwarm: High Throughput Model Checking on FPGAs S Cho, M Ferdman, P Milder 2018 28th International Conference on Field Programmable Logic and …, 2018 | 10 | 2018 |
| A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs S Cho, M Patel, H Chen, M Ferdman, P Milder Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 10 | 2018 |
| Waverunner: An Elegant Approach to Hardware Acceleration of State Machine Replication M Alimadadi, H Mai, S Cho, M Ferdman, P Milder, S Mu 20th USENIX Symposium on Networked Systems Design and Implementation (NSDI), 2023 | 7 | 2023 |
| Dynamic virtualized field-programmable gate array resource control for performance and reliability DA Roberts, S Cho US Patent 10,447,273, 2019 | 7 | 2019 |
| Runtime-Programmable Pipelines for Model Checkers on FPGAs M Patel, S Cho, M Ferdman, P Milder 2019 29th International Conference on Field Programmable Logic and …, 2019 | 4 | 2019 |
| Method to synchronize and synthesize bus transaction traces for an un-timed virtual environment HW Chang, PS Su, SH Cho US Patent App. 13/064,159, 2012 | 1 | 2012 |
| Practical Model Checking on FPGAs S Cho, M Patel, M Ferdman, P Milder ACM Transactions on Reconfigurable Technology and Systems (TRETS) 14 (2), 1-18, 2021 | | 2021 |
| Instructions for Performing Multi-Line Memory Accesses DA Roberts, S Cho US Patent 11,023,410, 2021 | | 2021 |
| Minimizing the Impact of Communication Latency between CPUs, Memory, and Accelerators S Cho State University of New York at Stony Brook, 2021 | | 2021 |
| Swarm Model Checking on the GPU SA Smolka Model Checking Software: 26th International Symposium, SPIN 2019, Beijing …, 2019 | | 2019 |
| A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs S Cho, M Patel, B Kaladagi, H Chen, T Palit, M Ferdman, P Milder Department of Computer Science, 2017 | | 2017 |
