| Predictive modeling of the NBTI effect for reliable design S Bhardwaj, W Wang, R Vattikonda, Y Cao, S Vrudhula IEEE Custom Integrated Circuits Conference 2006, 189-192, 2006 | 541 | 2006 |
| The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis W Wang, S Yang, S Bhardwaj, S Vrudhula, F Liu, Y Cao IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (2), 173-183, 2009 | 372 | 2009 |
| The impact of NBTI on the performance of combinational and sequential circuits W Wang, S Yang, S Bhardwaj, R Vattikonda, S Vrudhula, F Liu, Y Cao Proceedings of the 44th annual Design Automation Conference, 364-369, 2007 | 296 | 2007 |
| /spl tau/AU: Timing analysis under uncertainty S Bhardwaj, SBK Vrudhula, D Blaauw ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 88 | 2003 |
| A framework for statistical timing analysis using non-linear delay and slew models S Bhardwaj, P Ghanta, S Vrudhula Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 69 | 2006 |
| Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits S Bhardwaj, S Vrudhula, P Ghanta, Y Cao Proceedings of the 43rd annual Design Automation Conference, 791-796, 2006 | 66 | 2006 |
| Secure and robust localization in a wireless ad hoc environment S Misra, G Xue, S Bhardwaj IEEE Transactions on Vehicular Technology 58 (3), 1480-1489, 2008 | 56 | 2008 |
| Leakage minimization of nano-scale circuits in the presence of systematic and random variations S Bhardwaj, SBK Vrudhula Proceedings of the 42nd annual Design Automation Conference, 541-546, 2005 | 53 | 2005 |
| Scalable model for predicting the effect of negative bias temperature instability for reliable design S Bhardwaj, W Wang, R Vattikonda, Y Cao, S Vrudhula IET circuits, devices & systems 2 (4), 361-371, 2008 | 37 | 2008 |
| A unified approach for full chip statistical timing and leakage analysis of nanoscale circuits considering intradie process variations S Bhardwaj, S Vrudhula, A Goel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 31 | 2008 |
| Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage S Bhardwaj, Y Cao, S Vrudhula Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 27 | 2006 |
| Leakage minimization of digital circuits using gate sizing in the presence of process variations S Bhardwaj, S Vrudhula IEEE transactions on computer-aided design of integrated circuits and …, 2008 | 25 | 2008 |
| On timing closure: Buffer insertion for hold-violation removal PC Wu, MDF Wong, I Nedelchev, S Bhardwaj, V Parkhe Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 24 | 2014 |
| Fast Lagrangian relaxation-based multithreaded gate sizing using simple timing calibrations A Sharma, D Chinnery, T Reimann, S Bhardwaj, C Chu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 21 | 2019 |
| Fast Lagrangian relaxation based gate sizing using multi-threading A Sharma, D Chinnery, S Bhardwaj, C Chu 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 426-433, 2015 | 21 | 2015 |
| Temperature and process variations aware power gating of functional units D Kannan, A Shrivastava, V Mohan, S Bhardwaj, S Vrudhula 21st International Conference on VLSI Design (VLSID 2008), 515-520, 2008 | 19 | 2008 |
| ROSETTA: Robust and secure mobile target tracking in a wireless ad hoc environment S Misra, S Bhardwaj, G Xue MILCOM 2006-2006 IEEE Military Communications Conference, 1-7, 2006 | 18 | 2006 |
| Stochastic variational analysis of large power grids considering intra-die correlations P Ghanta, S Vrudhula, S Bhardwaj, R Panda Proceedings of the 43rd annual Design Automation Conference, 211-216, 2006 | 18 | 2006 |
| Clock-reconvergence pessimism removal in hierarchical static timing analysis S Bhardwaj, K Rahmat, K Kucukcakar US Patent 8,434,040, 2013 | 15 | 2013 |
| Reducing functional unit power consumption and its variation using leakage sensors A Shrivastava, D Kannan, S Bhardwaj, S Vrudhula IEEE transactions on very large scale integration (VLSI) systems 18 (6), 988-997, 2009 | 15 | 2009 |
