| BioMOCA—a Boltzmann transport Monte Carlo model for ion channel simulation TA Van der Straaten, G Kathawala, A Trellakis, RS Eisenberg §, ... Molecular Simulation 31 (2-3), 151-171, 2005 | 66 | 2005 |
| Monte Carlo simulations of double-gate MOSFETs GA Kathawala, B Winstead, U Ravaioli IEEE Transactions on electron devices 50 (12), 2467-2473, 2004 | 66 | 2004 |
| Comparison of Monte Carlo and NEGF simulations of double gate MOSFETs R Ravishankar, G Kathawala, U Ravaioli, S Hasan, M Lundstrom Journal of Computational Electronics 4, 39-43, 2005 | 26 | 2005 |
| System and method of managing data in a non-volatile memory having a staging sub-drive GA Kathawala, SA Gorobets, KS Stoev, JE Frayer, LM Parker US Patent 10,032,488, 2018 | 23 | 2018 |
| Programming in memory devices using source bitline voltage bias Z Liu, A Chen, W Zheng, KT Chang, SY Chung, GA Kathawala, ... US Patent 7,746,698, 2010 | 21 | 2010 |
| Recovery combining hard decoding, soft decoding and artificial codeword generation AN Jacobvitz, GA Kathawala, KS Stoev, B Wu US Patent 10,552,259, 2020 | 18 | 2020 |
| Method and System For Adaptively Adjusting a Verify Voltage to Reduce Storage Raw Bit Error Rate GA Kathawala, Y Zhang, W Chen, S Park US Patent App. 15/186,339, 2017 | 18 | 2017 |
| 3-D monte carlo simulations of FinFETs GA Kathawala, U Ravaioli IEEE International Electron Devices Meeting 2003, 29.2. 1-29.2. 4, 2003 | 17 | 2003 |
| Biomoca: A transport monte carlo model for ion channels T Van Der Straaten, G Kathawala, U Ravaioli Journal of Computational Electronics 2, 231-237, 2003 | 16 | 2003 |
| Comparison of double-gate MOSFETs and FinFETs with Monte Carlo simulation GA Kathawala, M Mohamed, U Ravaioli Journal of Computational Electronics 2, 85-89, 2003 | 14 | 2003 |
| Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb Y Mizuguchi, MW Randolph, DG Hamilton, Y He, Z Liu, YE Lin, X Yi, ... US Patent 7,995,386, 2011 | 12 | 2011 |
| Block management for data streams GA Kathawala, L Parker, K Stoev US Patent 10,338,841, 2019 | 10 | 2019 |
| Room temperature drift suppression via soft program after erase GR Jones, MW Randolph, J Darilek, S O'mullan, J Marcantel, R Anundson, ... US Patent 7,944,746, 2011 | 9 | 2011 |
| Device engineering approaches to the simulation of charge transport in biological ion channels TA van der Straaten, G Kathawala, U Ravaioli Journal of Computational and Theoretical Nanoscience 3 (1), 42-62, 2006 | 7 | 2006 |
| Equilibrium Structure of Electrolyte calculated using Equilibrium Monte Carlo, Molecular Dynamics, and Boltzmann Transport Monte Carlo Simulations TA Van Der Straaten, G Kathawala, Z Kuang, D Boda, DP Chen, ... 2003 Nanotechnology Conference and Trade Show-Nanotech 2003, 447-451, 2003 | 7 | 2003 |
| Changing storage parameters A Lee, YC Chen, A Koh, G Kathawala, M Kochar US Patent 10,014,056, 2018 | 6 | 2018 |
| Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory GA Kathawala, W Zheng, Z Liu, SY Chung, T Thurgate, KT Chang, ... US Patent 7,746,705, 2010 | 5 | 2010 |
| Monte Carlo simulation of nanostructures: Semiconductor devices to ion channels GA Kathawala University of Illinois at Urbana-Champaign, 2005 | 5 | 2005 |
| Parity storage management GA Kathawala, S Park, J Yuan, M Dancho US Patent 10,108,470, 2018 | 3 | 2018 |
| Multi-phase wordline erasing for flash memory X Wang, Y He, Z Liu, SY Chung, DG Hamilton, A Melik-Martirosian, ... US Patent 7,626,869, 2009 | 3 | 2009 |
