| Pruning and quantization for deep neural network acceleration: A survey T Liang, J Glossner, L Wang, S Shi, X Zhang Neurocomputing 461, 370-403, 2021 | 846 | 2021 |
| A software-defined communications baseband design J Glossner, D Iancu, J Lu, E Hokenek, M Moudgill IEEE Communications Magazine 41 (1), 120-128, 2003 | 183 | 2003 |
| Iterative concatenated convolutional Reed-Solomon decoding method D Iancu, H Ye, J Glossner US Patent 7,370,258, 2008 | 161 | 2008 |
| Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier GG Pechanek, LD Larsen, CJ Glossner, S Vassiliaadis, DH McCabe US Patent 5,682,491, 1997 | 144 | 1997 |
| Distributed processing array with component processors performing customized interpretation of instructions GG Pechanek, LD Larsen, CJ Glossner, S Vassiliaadis US Patent 6,128,720, 2000 | 125 | 2000 |
| The sandbridge sb3011 platform J Glossner, D Iancu, M Moudgill, G Nacer, S Jinturkar, S Stanley, ... EURASIP journal on embedded systems 2007 (1), 056467, 2007 | 84 | 2007 |
| Array processor communication architecture with broadcast processor instructions GG Pechanek, LD Larsen, CJ Glossner, S Vassiliaadis US Patent 5,659,785, 1997 | 82 | 1997 |
| Parallel processing system and method using surrogate instructions GG Pechanek, CJ Glossner, LD Larsen, S Vassiliadis US Patent 5,649,135, 1997 | 79 | 1997 |
| Vector register file with arbitrary vector addressing CJ Glossner III, E Hokenek, D Meltzer, M Moudgill US Patent 6,665,790, 2003 | 77* | 2003 |
| Modified printed dipole antennas for wireless multi-band communication systems E Surducan, D Iancu, J Glossner US Patent 7,034,769, 2006 | 76 | 2006 |
| Method and apparatus for token triggered multithreading E Hokenek, M Moudgill, CJ Glossner US Patent 6,842,848, 2005 | 56 | 2005 |
| A static low-power, high-performance 32-bit carry skip adder K Chirca, M Schulte, J Glossner, H Wang, B Mamidi, P Balzola, ... Euromicro Symposium on Digital System Design, 2004. DSD 2004., 615-619, 2004 | 54 | 2004 |
| Trends in compilable DSP architecture J Glossner, J Moreno, M Moudgill, J Derby, E Hokenek, D Meltzer, ... 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and …, 2000 | 54 | 2000 |
| The Delft-Java engine: An introduction CJ Glossner, S Vassiliadis Euro-Par'97 Parallel Processing: Third International Euro-Par Conference …, 1997 | 54 | 1997 |
| Method and apparatus for register file port reduction in a multithreaded processor E Hokenek, M Moudgill, CJ Glossner US Patent 6,904,511, 2005 | 53 | 2005 |
| Processor reduction unit for accumulation of multiple operands with or without saturation MJ Schulte, PI Balzola, CJ Glossner US Patent 7,593,978, 2009 | 48 | 2009 |
| A low-power multithreaded processor for software defined radio M Schulte, J Glossner, S Jinturkar, M Moudgill, S Mamidi, S Vassiliadis Journal of VLSI signal processing systems for signal, image and video …, 2006 | 47 | 2006 |
| Convergence device with dynamic program throttling that replaces noncritical programs with alternate capacity programs based on power indicator G Weinberger, CJ Glossner US Patent 7,251,737, 2007 | 44 | 2007 |
| Method and apparatus for thread-based memory access in a multithreaded processor E Hokenek, M Moudgill, CJ Glossner US Patent 6,925,643, 2005 | 42 | 2005 |
| Processor having parallel vector multiply and reduce operations with sequential semantics E Hokenek, MJ Schulte, M Moudgill, CJ Glossner US Patent 7,797,363, 2010 | 41 | 2010 |