| A formal approach for detecting vulnerabilities to transient execution attacks in out-of-order processors MR Fadiheh, J Müller, R Brinkmann, S Mitra, D Stoffel, W Kunz 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 51 | 2020 |
| An exhaustive approach to detecting transient execution side channels in RTL designs of processors MR Fadiheh, A Wezel, J Müller, J Bormann, S Ray, JM Fung, S Mitra, ... IEEE Transactions on Computers 72 (1), 222-235, 2022 | 27 | 2022 |
| A formal approach to confidentiality verification in SoCs at the register transfer level J Müller, MR Fadiheh, ALD Antón, T Eisenbarth, D Stoffel, W Kunz 2021 58th ACM/IEEE Design Automation Conference (DAC), 991-996, 2021 | 18 | 2021 |
| Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, and Wolfgang Kunz. 2022. An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of … MR Fadiheh, A Wezel, J Müller, J Bormann IEEE Trans. Comput 72 (1), 222-235, 2022 | 16 | 2022 |
| Towards a formally verified hardware root-of-trust for data-oblivious computing L Deutschmann, J Müller, MR Fadiheh, D Stoffel, W Kunz Proceedings of the 59th ACM/IEEE Design Automation Conference, 727-732, 2022 | 13 | 2022 |
| Fault attacks on access control in processors: Threat, formal analysis and microarchitectural mitigation ALD Antón, J Müller, MR Fadiheh, D Stoffel, W Kunz IEEE Access 11, 52695-52711, 2023 | 9 | 2023 |
| Design of Access Control Mechanisms in {Systems-on-Chip} with Formal Integrity Guarantees D Mehmedagić, MR Fadiheh, J Müller, ALD Antón, D Stoffel, W Kunz 32nd USENIX Security Symposium (USENIX Security 23), 2779-2796, 2023 | 7 | 2023 |
| A scalable formal verification methodology for data-oblivious hardware L Deutschmann, J Müller, MR Fadiheh, D Stoffel, W Kunz IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 6 | 2024 |
| A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators ALD Antón, J Müller, L Deutschmann, MR Fadiheh, D Stoffel, W Kunz 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024 | 2 | 2024 |
| UPEC-PN: Exhaustive constant time verification of low-level software using property checking P Schmitz, J Mueller, C Bartsch, D Stoffel, W Kunz MBMV 2023; 26th Workshop, 1-8, 2023 | 1 | 2023 |
| VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL ALD Antón, J Müller, P Schmitz, T Jauch, A Wezel, L Deutschmann, ... arXiv preprint arXiv:2407.18679, 2024 | | 2024 |
| MCU-Wide Timing Side Channels and Their Detection J Müller, AL Duque Antón, L Deutschmann, D Mehmedagić, C Rodrigues, ... Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024 | | 2024 |
| Data-Oblivious and Performant: On Designing Security-Conscious Hardware L Deutschmann, Y Kazhalawi, J Seckinger, ALD Antón, J Müller, ... 2024 IEEE 25th Latin American Test Symposium (LATS), 1-6, 2024 | | 2024 |
| A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators A Lena Duque Antón, J Müller, L Deutschmann, M Rahmani Fadiheh, ... arXiv e-prints, arXiv: 2312.06515, 2023 | | 2023 |
| A New Security Threat in MCUs--SoC-wide timing side channels and how to find them J Müller, ALD Antón, L Deutschmann, D Mehmedagić, MR Fadiheh, ... arXiv preprint arXiv:2309.12925, 2023 | | 2023 |
| LOS 2: FORMAL SECURITY VERIFICATION OF HARDWARE W Kunz, D Stoffel, J Müller, MR Fadiheh | | 2023 |
| An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors M Rahmani Fadiheh, A Wezel, J Mueller, J Bormann, S Ray, JM Fung, ... arXiv e-prints, arXiv: 2108.01979, 2021 | | 2021 |
Mohammad Rahmani FadihehStanford UniversityEmail verificata su stanford.edu