A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB AT Narayanan, M Katsuragi, K Kimura, S Kondo, KK Tokgoz, K Nakata, ...
IEEE Journal of Solid-State Circuits 51 (7), 1630-1640, 2016
146 2016 14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
65 2015 13.3 A 56Gb/s W-band CMOS wireless transceiver KK Tokgoz, S Maki, S Kawai, N Nagashima, J Emmei, M Dome, H Kato, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 242-243, 2016
61 2016 A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular T Siriburanon, H Liu, K Nakata, W Deng, JH Son, DY Lee, K Okada, ...
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
45 2015 A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration B Liu, Y Zhang, J Qiu, HC Ngo, W Deng, K Nakata, T Yoshioka, J Emmei, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 603-616, 2020
42 2020 8.5 A 0.42 ps-jitter− 241.7 dB-FOM synthesizable injection-locked PLL with noise-isolation LDO HC Ngo, K Nakata, T Yoshioka, Y Terashima, K Okada, A Matsuzawa
2017 IEEE International Solid-State Circuits Conference (ISSCC), 150-151, 2017
36 2017 Revisiting a knn-based image classification system with high-capacity storage K Nakata, Y Ng, D Miyashita, A Maki, YC Lin, J Deguchi
European Conference on Computer Vision, 457-474, 2022
29 2022 An 802.11ax 4 S Kawai, R Ito, K Nakata, Y Shimizu, M Nagata, T Takeuchi, H Kobayashi, ...
IEEE Journal of Solid-State Circuits 53 (12), 3688-3699, 2018
27 2018 A 1.2 ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ...
2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018
25 2018 An 802.11 ax 4× 4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer S Kawai, H Aoyama, R Ito, Y Shimizu, M Ashida, A Maki, T Takeuchi, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 442-444, 2018
18 2018 Fpga-based cnn processor with filter-wise-optimized bit precision A Maki, D Miyashita, K Nakata, F Tachibana, T Suzuki, J Deguchi
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 47-50, 2018
17 2018 A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ...
IEEE Solid-State Circuits Letters 2 (1), 5-8, 2019
16 2019 Adaptive quantization method for CNN with computational-complexity-aware regularization K Nakata, D Miyashita, J Deguchi, R Fujimoto
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
12 2021 A 0.048 mm 2 3 mW synthesizable fractional-N PLL with a soft injectionlocking technique W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ...
ISSCC Digest of Technical Papers 1, 2015
8 2015 Weight compression MAC accelerator for effective inference of deep learning A Maki, D Miyashita, S Sasaki, K Nakata, F Tachibana, T Suzuki, ...
IEICE Transactions on Electronics 103 (10), 514-523, 2020
4 2020 Can in-memory/analog accelerators be a silver bullet for energy-efficient inference? J Deguchi, D Miyashita, A Maki, S Sasaki, K Nakata, F Tachibana
2019 IEEE International Electron Devices Meeting (IEDM), 22.4. 1-22.4. 4, 2019
4 2019 An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection D Yang, W Deng, AT Narayanan, K Nakata, T Siriburanon, K Okada, ...
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 1-2, 2016
3 2016 Information processing apparatus for convolution operations in layers of convolutional neural network A Maki, D Miyashita, K Nakata, F Tachibana, J Deguchi, S Sasaki
US Patent App. 16/291,471, 2020
2 2020 Live demonstration: Fpga-based cnn accelerator with filter-wise-optimized bit precision K Nakata, A Maki, D Miyashita, F Tachibana, T Suzuki, J Deguchi
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2019
2 2019 Prune or quantize? strategy for pareto-optimally low-cost and accurate cnn K Nakata, D Miyashita, A Maki, F Tachibana, S Sasaki, J Deguchi
2 2019 