A fully-integrated low-dropout regulator with full-spectrum power supply rejection Y Lu, Y Wang, Q Pan, WH Ki, CP Yue
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (3), 707-716, 2015
227 2015 An 18-Gb/s fully integrated optical receiver with adaptive cascaded equalizer Q Pan, Y Wang, Y Lu, CP Yue
IEEE Journal of Selected Topics in Quantum Electronics 22 (6), 361-369, 2016
41 2016 8.5 a scalable adaptive ADC/DSP-based 1.25-to-56Gbps/112Gbps high-speed transceiver architecture using decision-directed MMSE CDR in 16nm and 7nm D Xu, Y Kou, P Lai, Z Cheng, TY Cheung, L Moser, Y Zhang, X Liu, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 134-136, 2021
37 2021 A 42-dB -Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications Q Pan, Y Wang, CP Yue
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (1), 72-76, 2019
35 2019 A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems Y Wang, Y Lu, Q Pan, Z Hou, L Wu, WH Ki, CP Yue
2014 IEEE Radio Frequency Integrated Circuits Symposium, 275-278, 2014
28 2014 A 30-Gb/s 1.37-pJ/b CMOS receiver for optical interconnects Q Pan, Y Wang, Z Hou, L Sun, Y Lu, WH Ki, P Chiang, CP Yue
Journal of Lightwave Technology 33 (4), 778-786, 2014
27 2014 A− 40° C to 120° C, 169 ppm/° C nano-ampere CMOS current reference Q Huang, C Zhan, L Wang, Z Li, Q Pan
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1494-1498, 2020
22 2020 A 56-Gb/s PAM4 receiver analog front-end with fixed peaking frequency and bandwidth in 40-nm CMOS Z Li, M Tang, T Fan, Q Pan
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (9), 3058-3062, 2021
21 2021 A 15-Gb/s 0.0037-mm² 0.019-pJ/bit full-rate programmable multi-pattern pseudo-random binary sequence generator J Hu, Z Zhang, Q Pan
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1499-1503, 2020
20 2020 A fully integrated 25 Gb/s low-noise TIA+ CDR optical receiver designed in 40-nm-CMOS J Wang, Q Pan, Y Qin, X Chen, S Hu, R Bai, X Wang, Y Cai, T Xia, ...
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (10), 1698-1702, 2019
18 2019 A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer Q Pan, Z Hou, Y Wang, Y Lu, WH Ki, KC Wang, CP Yue
2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014
16 2014 A 0.5-V P-well/deep N-well photodetector in 65-nm CMOS for monolithic 850-nm optical receivers Q Pan, Z Hou, Y Li, AW Poon, CP Yue
IEEE Photonics Technology Letters 26 (12), 1184-1187, 2014
16 2014 A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization Q Pan, Y Wang, Z Hou, L Sun, L Wu, WH Ki, P Chiang, CP Yue
ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 127-130, 2014
15 2014 A 23-mW 30-Gb/s digitally programmable limiting amplifier for 100GbE optical receivers Z Hou, Q Pan, Y Wang, L Wu, CP Yue
2014 IEEE Radio Frequency Integrated Circuits Symposium, 279-282, 2014
15 2014 A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications Q Pan, X Luo
Journal of Semiconductors 43 (1), 012401, 2022
14 2022 A 50Gb/s PAM-4 retimer-CDR+ VCSEL driver with asymmetric pulsed pre-emphasis integrated into a single CMOS die S Hu, T Yao, B Yin, C Song, L Zhao, J Wang, L Wang, R Bai, X Wang, ...
2019 Optical Fiber Communications Conference and Exhibition (OFC), 1-3, 2019
13 2019 A 54–68 GHz power amplifier with improved linearity and efficiency in 40 nm CMOS H Mosalam, W Xiao, X Gui, D Li, Q Pan
IEEE Transactions on Circuits and Systems II: Express Briefs 69 (1), 40-44, 2021
12 2021 An area-efficient low quiescent current output capacitor-less ldo with fast transient response H Qiao, C Zhan, Q Pan, Y Chen, N Zhang
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2021
12 2021 A 26–28-Gb/s full-rate clock and data recovery circuit with embedded equalizer in 65-nm CMOS L Sun, Q Pan, KC Wang, CP Yue
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (7), 2139-2149, 2014
12 2014 A 0.96-0.9-V fully integrated FVF LDO with two-stage cross-coupled error amplifier D Xu, Y Zhang, X Luo, Z Li, Q Pan
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
11 2023