| Divas: An llm-based end-to-end framework for soc security analysis and policy-based protection S Paria, A Dasgupta, S Bhunia arXiv preprint arXiv:2308.06932, 2023 | 24 | 2023 |
| Optimal design of 5.5 GHz CMOS LNA using hybrid fitness based adaptive De with PSO S Mallick, JR Akhil, A Dasgupta, R Kar, D Mandal, SP Ghoshal 2017 International Electrical Engineering Congress (iEECON), 1-4, 2017 | 9 | 2017 |
| Identification of a Box-Jenkins structured two stage cascaded model using simplex particle swarm optimization algorithm PS Pal, A Dasgupta, JR Akhil, R Kar, D Mandal, SP Ghosal 2016 International Symposium on Intelligent Signal Processing and …, 2016 | 3 | 2016 |
| Navigating SoC Security Landscape on LLM-Guided Paths S Paria, A Dasgupta, S Bhunia Proceedings of the Great Lakes Symposium on VLSI 2024, 252-257, 2024 | 2 | 2024 |
| An iteratively optimized resolution to hyper redundancy for dissimilarly doped compliant IPMC actuators R Chattaraj, S Khan, A Dasgupta, G Gare, D Chatterjee, S Bhaumik Mechatronics 46, 154-167, 2017 | 2 | 2017 |
| DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement S Paria, A Dasgupta, S Bhunia 2024 IEEE International Symposium on Hardware Oriented Security and Trust …, 2024 | 1 | 2024 |
| Timed unlocking and locking of hardware intellectual properties S Bhunia, A Alaql, A Dasgupta, MM Rahman US Patent 11,720,654, 2023 | 1 | 2023 |
| An exploration of ATPG methods for redacted IP and reconfigurable hardware J Fugate, G Stitt, NVR Masna, A Dasgupta, S Bhunia, N Dorairaj, D Kehlet 2023 IEEE 41st VLSI Test Symposium (VTS), 1-7, 2023 | 1 | 2023 |
| Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection A Dasgupta, S Paria, C Sozio, A Lukefahr, S Bhunia arXiv preprint arXiv:2501.12292, 2025 | | 2025 |
| SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems S Paria, A Dasgupta, S Bhunia IEEE Embedded Systems Letters 16 (4), 365-368, 2024 | | 2024 |
| United We Protect: Protecting IP Confidentiality with Integrated Transformation and Redaction MM Rahman, R Almawzan, A Dasgupta, S Paria, S Bhunia 2024 IEEE Physical Assurance and Inspection of Electronics (PAINE), 1-7, 2024 | | 2024 |
| FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices SD Paul, A Dasgupta, S Bhunia IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2024 | | 2024 |
| IP Security in Structured ASIC: Challenges and Prospects R Almawzan, S Paria, A Dasgupta, K Amberiadis, S Bhunia 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 397-402, 2024 | | 2024 |
| Pasteables: A Flexible, Stick-and-Peel Smart Sensing Platform for Edge Applications R Dizon-Paradis, A Dasgupta, RR Kalavakonda, S Bhunia 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 539-543, 2024 | | 2024 |
| Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs A Dasgupta, S Paria, P Chakraborty, S Bhunia 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 325-330, 2024 | | 2024 |
| Automated test pattern generation for testing design redacting reconfigurable hardware GM Stitt, S Bhunia, NVR Masna, A Dasgupta US Patent App. 18/536,973, 2024 | | 2024 |
| LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations R Almawzan, A Chatterjee, A Dasgupta, S Bhunia Proceedings of the Great Lakes Symposium on VLSI 2024, 588-591, 2024 | | 2024 |
| Multi-layered framework for security of integrated circuits S Bhunia, A Dasgupta, R Dizon, A Bhattacharyay, R Almawzan US Patent App. 18/327,342, 2023 | | 2023 |
| Programmable application-specific array for protecting confidentiality and integrity of hardware ips S Bhunia, A Dasgupta, P Gaikwad, MM Rahman, A Bhattacharyay US Patent App. 17/808,179, 2023 | | 2023 |
| Decommissioning and erasing entropy in microelectronic systems S Bhunia, MM Rahman, A Dasgupta, A Alaql US Patent App. 17/573,053, 2022 | | 2022 |
