| Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach H Kwon, P Chatarasi, M Pellauer, A Parashar, V Sarkar, T Krishna Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 350 | 2019 |
| Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings H Kwon, P Chatarasi, V Sarkar, T Krishna, M Pellauer, A Parashar IEEE micro 40 (3), 20-29, 2020 | 201 | 2020 |
| Marvel: A data-centric approach for mapping deep learning operators on spatial accelerators P Chatarasi, H Kwon, A Parashar, M Pellauer, T Krishna, V Sarkar ACM Transactions on Architecture and Code Optimization (TACO) 19 (1), 1-26, 2021 | 64* | 2021 |
| An Extended Polyhedral Model for SPMD Programs and Its Use in Static Data Race Detection P Chatarasi, J Shirako, M Kong, V Sarkar Languages and Compilers for Parallel Computing: 29th International Workshop …, 2017 | 49 | 2017 |
| Polyhedral optimizations of explicitly parallel programs P Chatarasi, J Shirako, V Sarkar 2015 International Conference on Parallel Architecture and Compilation (PACT …, 2015 | 38 | 2015 |
| Evaluating spatial accelerator architectures with tiled matrix-matrix multiplication GE Moon, H Kwon, G Jeong, P Chatarasi, S Rajamanickam, T Krishna IEEE Transactions on Parallel and Distributed Systems 33 (4), 1002-1014, 2021 | 29 | 2021 |
| Union: A unified HW-SW co-design ecosystem in MLIR for evaluating tensor operations on spatial accelerators G Jeong, G Kestor, P Chatarasi, A Parashar, PA Tsai, S Rajamanickam, ... 2021 30th International Conference on Parallel Architectures and Compilation …, 2021 | 20 | 2021 |
| Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine P Chatarasi, S Neuendorffer, S Bayliss, K Vissers, V Sarkar 2020 IEEE High Performance Extreme Computing Conference (HPEC), 1-10, 2020 | 19 | 2020 |
| Experimental insights from the rogues gallery JS Young, J Riedy, TM Conte, V Sarkar, P Chatarasi, S Srikanth 2019 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2019 | 15 | 2019 |
| Static Data Race Detection for SPMD Programs via an Extended Polyhedral Representation P Chatarasi, J Shirako, M Kong, V Sarkar 6th International Workshop on Polyhedral Compilation Techniques (IMPACT’16), 2016 | 12 | 2016 |
| Hardware Abstractions for targeting EDDO Architectures with the Polyhedral Model A Parashar, P Chatarasi, PA Tsai IMPACT 2021, 11th International Workshop on Polyhedral Compilation Techniques, 2021 | 9 | 2021 |
| A preliminary study of compiler transformations for graph applications on the Emu system P Chatarasi, V Sarkar Proceedings of the Workshop on Memory Centric High Performance Computing, 37-44, 2018 | 9 | 2018 |
| Polyhedral transformations of explicitly parallel programs P Chatarasi, J Shirako, V Sarkar 5th International Workshop on Polyhedral Compilation Techniques (IMPACT) 90, 130, 2015 | 7 | 2015 |
| A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching J Tong, A Itagi, P Chatarasi, T Krishna ACM/IEEE Annual International Symposium on Computer Architecture, 2024 | 4* | 2024 |
| A unified approach to variable renaming for enhanced vectorization P Chatarasi, J Shirako, A Cohen, V Sarkar International Workshop on Languages and Compilers for Parallel Computing, 1-20, 2018 | 4 | 2018 |
| Generation of vector codes for tensor convolutions SA Neuendorffer, P Chatarasi, SR Bayliss US Patent 11,422,781, 2022 | 2 | 2022 |
| Extending Polyhedral Model for Analysis and Transformation of OpenMP Programs P Chatarasi, V Sarkar 2015 International Conference on Parallel Architecture and Compilation (PACT …, 2015 | 2 | 2015 |
| 14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC M Kar, J Silberman, S Venkataramani, V Srinivasan, B Fleischer, J Rubin, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 254-256, 2024 | 1 | 2024 |
| Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC M Kar, J Silberman, S Venkataramani, V Srinivasan, B Fleischer, J Rubin, ... IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| Optimal Placement of Hardware State-Changing Instructions B Mahjour, P Chatarasi, W Wang IP.com Prior Art Database (PAD), 2024 | | 2024 |
Vivek SarkarSchool of Computer Science, Georgia Institute of TechnologyEmail verificata su gatech.edu