Vertical silicon nanowire gate-all-around field effect transistor based nanoscale CMOS S Maheshwaram, SK Manhas, G Kaushal, B Anand, N Singh
IEEE electron device letters 32 (8), 1011-1013, 2011
47 2011 Radiation effects in Si-NW GAA FET and CMOS inverter: A TCAD simulation study G Kaushal, SS Rathod, S Maheshwaram, SK Manhas, AK Saxena, ...
IEEE Transactions on Electron Devices 59 (5), 1563-1566, 2012
43 2012 Electron transport in C3N monolayer: DFT analysis of volatile organic compound sensing S Agrawal, G Kaushal, A Srivastava
Chemical Physics Letters 762, 138121, 2021
32 2021 A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers R Shankar, G Kaushal, S Maheshwaram, S Dasgupta, SK Manhas
IEEE Transactions on Device and Materials Reliability 14 (2), 689-697, 2014
32 2014 Vertical nanowire CMOS parasitic modeling and its performance analysis S Maheshwaram, SK Manhas, G Kaushal, B Anand, N Singh
IEEE transactions on electron devices 60 (9), 2943-2950, 2013
32 2013 Single-event multiple effect tolerant RHBD14T SRAM cell design for space applications NR Ch, B Gupta, G Kaushal
IEEE Transactions on Device and Materials Reliability 21 (1), 48-56, 2021
30 2021 Double node upset tolerant RHBD15T SRAM cell design for space applications CHN Raghuram, B Gupta, G Kaushal
IEEE Transactions on Device and Materials Reliability 20 (1), 181-190, 2020
22 2020 Three-dimensional route planning for multiple unmanned aerial vehicles using Salp Swarm Algorithm RK Dewangan, P Saxena
Journal of Experimental & Theoretical Artificial Intelligence 35 (7), 1059-1078, 2023
21 2023 Impact of series resistance on Si nanowire MOSFET performance G Kaushal, SK Manhas, S Maheshwaram, S Dasgupta
Journal of Computational Electronics 12, 306-315, 2013
19 2013 Device circuit co-design issues in vertical nanowire CMOS platform S Maheshwaram, SK Manhas, G Kaushal, B Anand, N Singh
IEEE electron device letters 33 (7), 934-936, 2012
19 2012 Edge engineered graphene nanoribbons as nanoscale interconnect: DFT analysis S Agrawal, A Srivastava, G Kaushal, A Srivastava
IEEE Transactions on Nanotechnology 21, 43-51, 2022
17 2022 An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture N Srivastava, AK Rajput, M Pattanaik, G Kaushal
2023 36th International Conference on VLSI Design and 2023 22nd …, 2023
15 2023 Music genre classification using convolutional recurrent neural networks N Srivastava, S Ruhil, G Kaushal
2022 IEEE 6th Conference on Information and Communication Technology (CICT), 1-5, 2022
13 2022 Semantic image completion and enhancement using deep learning V Chandak, P Saxena, M Pattanaik, G Kaushal
2019 10th International Conference on Computing, Communication and …, 2019
12 2019 Low power SRAM design for 14 nm GAA Si-nanowire technology G Kaushal, H Jeong, S Maheshwaram, SK Manhas, S Dasgupta, SO Jung
Microelectronics Journal 46 (12), 1239-1247, 2015
11 2015 Novel Design Methodology Using G Kaushal, SK Manhas, S Maheshwaram, B Anand, S Dasgupta, N Singh
IEEE Transactions on Nanotechnology 13 (4), 650-658, 2014
10 2014 Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture AK Rajput, M Pattanaik, G Kaushal
Microelectronics Journal 129, 105569, 2022
9 2022 Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs G Kaushal, K Subramanyam, SN Rao, G Vidya, R Ramya, S Shaik, ...
2014 International SoC Design Conference (ISOCC), 32-33, 2014
9 2014 Design high frequency phase locked loop using single ended VCO for high speed applications R Ahirwar, HK Shankhwar, G Kaushal, M Pattanaik, P Srivastava
2022 IEEE Conference on Interdisciplinary Approaches in Technology and …, 2022
7 2022 An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor AK Rajput, M Pattanaik, G Kaushal
Memories-Materials, Devices, Circuits and Systems 5, 100076, 2023
6 2023