Process-variation-calibrated multiphase delay locked loop with a loop-embedded duty cycle corrector K Ryu, DH Jung, SO Jung
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (1), 1-5, 2013
73 2013 A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator K Ryu, DH Jung, SO Jung
IEEE Transactions on Circuits and Systems I: Regular Papers 59 (9), 1860-1870, 2012
56 2012 An energy efficient time-domain temperature sensor for low-power on-chip thermal management YJ An, K Ryu, DH Jung, SH Woo, SO Jung
IEEE sensors journal 14 (1), 104-110, 2013
42 2013 0.293-mm2 Fast Transient Response Hysteretic Quasi- DH Jung, K Kim, S Joo, SO Jung
IEEE Journal of Solid-State Circuits 53 (6), 1844-1855, 2018
35 2018 Process Variation Tolerant All-Digital 90 H Kang, K Ryu, DH Jung, D Lee, W Lee, S Kim, J Choi, SO Jung
IEEE Transactions on Circuits and Systems I: Regular Papers 59 (10), 2186-2196, 2012
30 2012 All-digital on-chip process sensor using ratioed inverter-based ring oscillator YJ An, DH Jung, K Ryu, HS Yim, SO Jung
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (11 …, 2016
28 2016 29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm … DH Jung, TH Kong, JH Yang, SH Kim, K Kim, J Park, M Choi, J Shin
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 414-416, 2021
23 2021 Delay locked loop and method of generating clock SO Jung, DH Jung, K Ryu, JH Park
US Patent 9,035,684, 2015
22 2015 An energy-efficient all-digital time-domain-based CMOS temperature sensor for SoC thermal management YJ An, DH Jung, K Ryu, SH Woo, SO Jung
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (8 …, 2014
21 2014 All-digital fast-locking delay-locked loop using a cyclic-locking loop for DRAM DH Jung, YJ An, K Ryu, JH Park, SO Jung
IEEE Transactions on Circuits and Systems II: Express Briefs 62 (11), 1023-1027, 2015
20 2015 Digital DLL including skewed gate type duty correction circuit and duty correction method thereof W Lee, D Lee, SO Jung, H Kang, K Ryu, D Jung
US Patent 8,519,758, 2013
20 2013 High-speed, low-power, and highly reliable frequency multiplier for DLL-based clock generator K Ryu, J Jung, DH Jung, JH Kim, SO Jung
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (4 …, 2015
19 2015 Delay locked loop DH Jung, J Kim, KH Ryu, SO Jung, BC Oh
US Patent 9,154,140, 2015
16 2015 All-digital 90° phase-shift DLL with dithering jitter suppression scheme DH Jung, K Ryu, JH Park, SO Jung
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (3 …, 2015
16 2015 All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate K Ryu, DH Jung, SO Jung
2013 Proceedings of the ESSCIRC (ESSCIRC), 41-44, 2013
14 2013 A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction DH Jung, K Ryu, JH Park, SO Jung
2012 Proceedings of the ESSCIRC (ESSCIRC), 181-184, 2012
13 2012 Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm DH Jung, K Kim, SO Jung
ieice electronics express 13 (12), 20160287-20160287, 2016
12 2016 All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and maximum 1.2-GHz test rate DH Jung, K Ryu, JH Park, SO Jung
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (6 …, 2018
11 2018 ADDLL for clock-deskew buffer in high-performance SoCs JH Park, DH Jung, K Ryu, SO Jung
IEEE transactions on very large scale integration (VLSI) systems 21 (7 …, 2012
10 2012 GRO‐TDC with gate‐switch‐based delay cell halving resolution limit JH Park, DH Jung, SO Jung
International Journal of Circuit Theory and Applications 45 (12), 2211-2225, 2017
6 2017 