Design solutions for sample-and-hold circuits in CMOS nanometer technologies F Centurelli, P Monsurro, S Pennisi, G Scotti, A Trifiletti
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (6), 459-463, 2009
64 2009 Efficient digital background calibration of time-interleaved pipeline analog-to-digital converters F Centurelli, P Monsurro, A Trifiletti
IEEE Transactions on Circuits and Systems I: Regular Papers 59 (7), 1373-1383, 2012
54 2012 Linearization technique for source-degenerated CMOS differential transconductors P Monsurro, S Pennisi, G Scotti, A Trifiletti
IEEE Transactions on Circuits and Systems II: Express Briefs 54 (10), 848-852, 2007
51 2007 88- G Scotti, S Pennisi, P Monsurrò, A Trifiletti
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (7), 1905-1916, 2014
47 2014 Behavioral modeling for calibration of pipeline analog-to-digital converters F Centurelli, P Monsurro, A Trifiletti
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (6), 1255-1264, 2010
43 2010 0.9‐V CMOS cascode amplifier with body‐driven gain boosting P Monsurro, S Pennisi, G Scotti, A Trifiletti
International Journal of Circuit Theory and Applications 37 (2), 193-202, 2009
42 2009 Secure double rate registers as an RTL countermeasure against power analysis attacks D Bellizia, S Bongiovanni, P Monsurrò, G Scotti, A Trifiletti, FB Trotta
IEEE transactions on very large scale integration (vlsi) systems 26 (7 …, 2018
41 2018 Exploiting the body of MOS devices for high performance analog design P Monsurro, S Pennisi, G Scotti, A Trifiletti
IEEE Circuits and Systems Magazine 11 (4), 8-23, 2011
41 2011 A topology of fully differential class-AB symmetrical OTA with improved CMRR F Centurelli, P Monsurrò, G Parisi, P Tommasino, A Trifiletti
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (11), 1504-1508, 2017
37 2017 Biasing technique via bulk terminal for minimum supply CMOS amplifiers P Monsurrò, G Scotti, A Trifiletti, S Pennisi
Electronics Letters 41 (14), 779-780, 2005
37 2005 Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications D Bellizia, S Bongiovanni, P Monsurrò, G Scotti, A Trifiletti
IEEE transactions on Emerging topics in Computing 5 (3), 329-339, 2016
35 2016 Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS M Avoli, F Centurelli, P Monsurrò, G Scotti, A Trifiletti
AEU-International Journal of Electronics and Communications 92, 30-35, 2018
33 2018 Analysis and implementation of a minimum-supply body-biased CMOS differential amplifier cell AD Grasso, P Monsurro, S Pennisi, G Scotti, A Trifiletti
IEEE transactions on very large scale integration (VLSI) systems 17 (2), 172-180, 2008
33 2008 New models for the calibration of four-channel time-interleaved ADCs using filter banks P Monsurrò, F Rosato, A Trifiletti
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (2), 141-145, 2017
31 2017 A class-AB flipped voltage follower output stage F Centurelli, P Monsurrò, A Trifiletti
2011 20th European Conference on Circuit Theory and Design (ECCTD), 757-760, 2011
31 2011 Improved digital background calibration of time-interleaved pipeline A/D converters F Centurelli, P Monsurro, A Trifiletti
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (2), 86-90, 2013
30 2013 A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate F Centurelli, R Della Sala, P Monsurrò, G Scotti, A Trifiletti
Journal of Low Power Electronics and Applications 11 (2), 19, 2021
27 2021 0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias D Cellucci, F Centurelli, V Di Stefano, P Monsurrò, S Pennisi, G Scotti, ...
International Journal of Circuit Theory and Applications 48 (1), 15-27, 2020
27 2020 Calibration of time-interleaved ADCs via Hermitianity-preserving Taylor approximations P Monsurrò, A Trifiletti
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (4), 357-361, 2016
26 2016 An ultra-low-voltage class-AB OTA exploiting local CMFB and body-to-gate interface F Centurelli, R Della Sala, P Monsurro, P Tommasino, A Trifiletti
AEU-International Journal of Electronics and Communications 145, 154081, 2022
24 2022 