| Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies R Rajaei, B Asgari, M Tabandeh, M Fazeli IEEE Transactions on Device and Materials Reliability 15 (3), 429 - 436, 2015 | 96 | 2015 |
| Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation R Rajaei, M Tabandeh, M Fazeli Microelectronics Reliability 53 (6), 912-924, 2013 | 70 | 2013 |
| Radiation Hardened Design of Nonvolatile MRAM-based FPGA R Rajaei IEEE Transactions on Magnetics (TMAG), 2016 | 64 | 2016 |
| Fully Nonvolatile and Low Power Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction with Spin-Hall Effect Assistance A Amirany, R Rajaei IEEE Transactions on Magnetics, 2018 | 59 | 2018 |
| Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations R Rajaei, M Tabandeh, M Fazeli Journal of Circuits, Systems and Computers 24 (01), 1550007, 2015 | 59 | 2015 |
| A Variation-Aware Ternary Spin-Hall Assisted STT-RAM Based on Hybrid MTJ/GAA-CNTFET Logic F Razi, MH Moaiyeri, R Rajaei, S Mohammadi IEEE Transactions on Nanotechnology, 2019 | 58 | 2019 |
| Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design R Rajaei, S Bakhtavari Mamaghani IEEE Transactions on Device and Materials Reliability (TDMR), 2017 | 50 | 2017 |
| In-memory computing with associative memories: A cross-layer perspective XS Hu, M Niemier, A Kazemi, AF Laguna, K Ni, R Rajaei, MM Sharifi, ... 2021 IEEE International Electron Devices Meeting (IEDM), 25.2. 1-25.2. 4, 2021 | 49 | 2021 |
| In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories A Kazemi, MM Sharifi, AF Laguna, F Müller, R Rajaei, R Olivo, T Kämpfe, ... Design, Automation and Test in Europe Conference (DATE'21), 2021 | 46 | 2021 |
| Nonvolatile, Spin-Based, and Low-Power Inexact Full Adder Circuits for Computing-in-Memory Image Processing A Amirany, R Rajaei SPIN, 2019 | 40 | 2019 |
| A novel hybrid algorithm for creating self-organizing fuzzy neural networks O Khayat, MM Ebadzadeh, HR Shahdoosti, R Rajaei, I Khajehnasiri Neurocomputing 73 (1-3), 517-524, 2009 | 39 | 2009 |
| Single event upset immune latch circuit design using C-element R Rajaei, M Tabandeh, B Rashidian 2011 9th IEEE International Conference on ASIC, 252-255, 2011 | 38 | 2011 |
| Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop A Amirany, F Marvi, K Jafari, R Rajaei IEEE Transactions on Nanotechnology, 2019 | 37 | 2019 |
| Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology R Rajaei, B Asgari, M Tabandeh, M Fazeli Turkish Journal of Electrical Engineering & Computer Sciences, 2016 | 36 | 2016 |
| Soft Error-Tolerant Design of MRAM-based Non-Volatile Latches for Sequential Logics R Rajaei, M Fazeli, M Tabandeh IEEE Transactions on Magnetics (TMAG) 51 (6), 2014 | 35 | 2014 |
| Compact Single-Phase-Search Multi-State Content Addressable Memory Design using 1 FeFET/Cell R Rajaei, MM Sharifi, A Kazemi, M Niemier, XS Hu IEEE Transaction on Electron Devices, 2021 | 34 | 2021 |
| Nonvolatile Low-Cost Approximate Spintronic Full-Adders for Computing-in-Memory Architectures R Rajaei, A Amirany IEEE Transactions on Magnetics, 2020 | 33 | 2020 |
| A Low-Cost and Highly Reliable Spintronics True Random Number Generator Circuit for Secure Cryptography I Alibeigi, A Amirany, R Rajaei, M Tabandeh, S Bagheri Shouraki SPIN, 2019 | 30 | 2019 |
| A Reconfigurable FeFET Content Addressable Memory For Multi-State Hamming Distance L Liu, AF Laguna, R Rajaei, MM Sharifi, A Kazemi, X Yin, M Niemier, ... IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 28 | 2023 |
| Single Event Double Node Upset Tolerance in MOS/Spintronic Sequential and Combinational Logic Circuits R Rajaei Microelectronics Reliability (MR), 2017 | 27 | 2017 |
Xiaobo Sharon HuUniversity of Notre Dame, Department of Computer Science and EngineeringEmail verificata su nd.edu