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Calvin Deutschbein
Calvin Deutschbein
Computer Science, School of Computing and Informationn Sciences, Willamette University
Email verificata su willamette.edu - Home page
Titolo
Citata da
Citata da
Anno
End-to-end automated exploit generation for validating the security of processor designs
R Zhang, C Deutschbein, P Huang, C Sturton
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
742018
Isadora: Automated Information Flow Property Generation for Hardware Designs
C Deutschbein, A Meza, F Restuccia, R Kastner, C Sturton
Proceedings of the 5th Workshop on Attacks and Solutions in Hardware …, 2021
192021
Performance and energy limits of a processor-integrated fft accelerator
T Thanh-Hoang, A Shambayati, C Deutschbein, H Hoffmann, AA Chien
2014 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2014
192014
Multi-core cyclic executives for safety-critical systems
C Deutschbein, T Fleming, A Burns, S Baruah
Science of Computer Programming 172, 102-116, 2019
182019
Mining security critical linear temporal logic specifications for processors
C Deutschbein, C Sturton
2018 19th International Workshop on Microprocessor and SOC Test and …, 2018
152018
Toward Hardware Security Property Generation at Scale
C Deutschbein, A Meza, F Restuccia, M Gregoire, R Kastner, C Sturton
IEEE Security & Privacy 20 (3), 43-51, 2022
102022
Evaluating Security Specification Mining for a CISC Architecture
C Deutschbein, C Sturton
2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020
82020
Isadora: automated information-flow property generation for hardware security verification
C Deutschbein, A Meza, F Restuccia, R Kastner, C Sturton
Journal of Cryptographic Engineering 13 (4), 391-407, 2023
62023
End-to-End Automated Exploit Generation for Processor Security Validation
R Zhang, C Deutschbein, P Huang, C Sturton
IEEE Design & Test 38 (3), 22-30, 2021
32021
Special Session: CAD for Hardware Security-Promising Directions for Automation of Security Assurance
S Aftabjahani, M Tehranipoor, F Farahmandi, B Ahmed, R Kastner, ...
2023 IEEE 41st VLSI Test Symposium (VTS), 1-10, 2023
22023
Mining Secure Behavior of Hardware Designs
C Deutschbein
The University of North Carolina at Chapel Hill, 2021
22021
A methodology for creating information–flow specifications of hardware designs
C Deutschbein, A Meza, F Restuccia, R Kastner, C Sturton
CoRR, 2021
12021
Preemptive Uniprocessor EDF Schedulability Analysis with Preemption Costs Considered.
C Deutschbein, SK Baruah
RTSS, 368, 2016
2016
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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