Daniel Ziener

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Jürgen TeichFull Professor, Computer Science, Friedrich-Alexander-Universität Erlangen-NürnbergEmail verificata su cs.fau.de
Dirk KochSchool of Computer Science, University of ManchesterEmail verificata su recobus.de
Stefan WildermannFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)Email verificata su fau.de
Frank HannigFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)Email verificata su cs.fau.de
Klaus Meyer-WegenerProfessor of Computer Science, Friedrich-Alexander-Universität Erlangen-NürnbergEmail verificata su fau.de
Jorge EchavarriaLeibniz Supercomputing CentreEmail verificata su lrz.de
Robért GleinFPGA Expert (SAR) at Capella SpaceEmail verificata su colorado.edu
Florian RittnerEmail verificata su fau.de
Felix ReimannAudi Electronics Venture GmbHEmail verificata su fex-it.de
Norbert WehnUniversity of KaiserslauternEmail verificata su eit.uni-kl.de
Andreas HerkersdorfProfessor for Electrical and Computer EngineeringEmail verificata su tum.de
Jim TorresenProfessor University of OsloEmail verificata su ifi.uio.no
Michael GlaßProfessor at Ulm UniversityEmail verificata su uni-ulm.de
Rolf ErnstProfessor at Institute of Computer and Network Engineering, TU Braunschweig, GermanyEmail verificata su tu-bs.de
Oliver BringmannProfessor of Embedded Systems, Eberhard Karls Universität Tübingen, GermanyEmail verificata su uni-tuebingen.de
Andreas WeichslgartnerCARIAD SEEmail verificata su cariad.technology
Kimon KarrasAMDEmail verificata su amd.com
Michaela BlottAMD ResearchEmail verificata su amd.com
Peter AthanasEmeritus Professor of Electrical and Computer EngineeringEmail verificata su vt.edu
Ingrid VerbauwhedeKU LeuvenEmail verificata su esat.kuleuven.be

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Daniel Ziener

Professor for Computer Architecture and Embedded Systems, Technische Universität Ilmenau

Email verificata su tu-ilmenau.de - Home page

Reconfigurable Computing FPGA Embedded Systems Reliability Security


Titolo Ordina per citazioni Ordina per anno Ordina per titolo	Citata da Citata da	Anno
On-the-fly composition of FPGA-based SQL query accelerators using a partially reconfigurable module library C Dennl, D Ziener, J Teich 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012	106	2012
FPGAs for software programmers D Koch, F Hannig, D Ziener Springer, 2016	99	2016
Power signature watermarking of IP cores for FPGAs D Ziener, J Teich Journal of Signal Processing Systems 51, 123-136, 2008	94	2008
FPGA-based dynamically reconfigurable SQL query processing D Ziener, F Bauer, A Becher, C Dennl, K Meyer-Wegener, U Schürfeld, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (4), 1-24, 2016	73	2016
Acceleration of SQL restrictions and aggregations through FPGA-based dynamic partial reconfiguration C Dennl, D Ziener, J Teich 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013	71	2013
Identifying FPGA IP-cores based on lookup table content analysis D Ziener, S Aßmus, J Teich 2006 international conference on field programmable logic and applications, 1-6, 2006	71	2006
Netlist-level IP protection by watermarking for LUT-based FPGAs M Schmid, D Ziener, J Teich 2008 International Conference on Field-Programmable Technology, 209-216, 2008	69	2008
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration A Becher, F Bauer, D Ziener, J Teich 2014 24th International Conference on Field Programmable Logic and …, 2014	61	2014
Partial reconfiguration on FPGAs in practice—Tools and applications D Koch, J Torresen, C Beckhoff, D Ziener, C Dennl, V Breuer, J Teich, ... ARCS 2012, 1-12, 2012	59	2012
A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor R Glein, B Schmidt, F Rittner, J Teich, D Ziener 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014	48	2014
A co-design approach for accelerated SQL query processing via FPGA-based data filtering A Becher, D Ziener, K Meyer-Wegener, J Teich 2015 International Conference on Field Programmable Technology (FPT), 192-195, 2015	46	2015
Using the power side channel of FPGAs for communication D Ziener, F Baueregger, J Teich 2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010	39	2010
FPGA core watermarking based on power signature analysis D Ziener, J Teich 2006 IEEE International Conference on Field Programmable Technology, 205-212, 2006	33	2006
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy R Glein, F Rittner, A Becher, D Ziener, J Frickel, J Teich, A Heuberger 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 1-8, 2015	30	2015
Throughput optimizations for FPGA-based deep neural network inference T Posewsky, D Ziener Microprocessors and microsystems 60, 151-161, 2018	29	2018
A dynamic reconfigurable architecture for hybrid spiking and convolutional fpga-based neural network designs H Irmak, F Corradi, P Detterer, N Alachiotis, D Ziener Journal of Low Power Electronics and Applications 11 (3), 32, 2021	28	2021
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs J Echavarria, S Wildermann, A Becher, J Teich, D Ziener 2016 International Conference on Field-Programmable Technology (FPT), 213-216, 2016	28	2016
Symbolic design space exploration for multi-mode reconfigurable systems S Wildermann, F Reimann, D Ziener, J Teich Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011	28	2011
Stress-aware module placement on reconfigurable devices J Angermeier, D Ziener, M Glaß, J Teich 2011 21st International Conference on Field Programmable Logic and …, 2011	27	2011
Increasing flexibility of FPGA-based CNN accelerators with dynamic partial reconfiguration H Irmak, D Ziener, N Alachiotis 2021 31st International Conference on Field-Programmable Logic and …, 2021	26	2021

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