| An accelerator for sparse convolutional neural networks leveraging systolic general matrix-matrix multiplication M Soltaniyeh, RP Martin, S Nagarakatte ACM Transactions on Architecture and Code Optimization (TACO) 19 (3), 1-26, 2022 | 23 | 2022 |
| Near-storage processing for solid state drive based recommendation inference with smartssds® M Soltaniyeh, V Lagrange Moutinho Dos Reis, M Bryson, X Yao, ... Proceedings of the 2022 ACM/SPEC on International Conference on Performance …, 2022 | 18 | 2022 |
| Synergistic CPU-FPGA acceleration of sparse linear algebra M Soltaniyeh, RP Martin, S Nagarakatte arXiv preprint arXiv:2004.13907, 2020 | 15 | 2020 |
| Quota setting router architecture for quality of service in GALS NoC K Cheshmi, J Trajkovic, M Soltaniyeh, S Mohammadi 2013 International Symposium on Rapid System Prototyping (RSP), 44-50, 2013 | 15 | 2013 |
| Near-storage acceleration of database query processing with SmartSSDs M Soltaniyeh, VLM Dos Reis, M Bryson, R Martin, S Nagarakatte 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021 | 9 | 2021 |
| Classifying data blocks at subpage granularity with an on-chip page table to improve coherence in tiled cmps M Soltaniyeh, I Kadayif, O Ozturk IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 7 | 2017 |
| SPOTS: An accelerator for sparse CNNs leveraging general matrix-matrix multiplication M Soltaniyeh, RP Martin, S Nagarakatte arXiv preprint arXiv:2107.13386, 2021 | 4 | 2021 |
| Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table M Soltaniyeh, I Kadayif, O Ozturk Proceedings of the ACM International Conference on Computing Frontiers, 180-187, 2016 | 2 | 2016 |
| ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model H Chen, Y Wang, V Cargnini, M Soltaniyeh, D Li, G Sun, P Subedi, ... Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024 | 1 | 2024 |
| Convolutional neural network accelerator hardware S Nagarakatte, RP Martin, M Soltaniyeh US Patent App. 18/198,579, 2023 | 1 | 2023 |
| SPOTS: An Accelerator for Sparse Convolutional Networks Leveraging Systolic General Matrix-Matrix Multiplication M Soltaniyeh, RP Martin, S Nagarakatte arXiv preprint arXiv:2107.13386, 2021 | 1 | 2021 |
| SYSTEMS AND METHODS FOR PARALLEL DATA PROCESSING M Soltaniyeh, X Yao, R Kachare US Patent App. 18/506,993, 2024 | | 2024 |
| Device cache engine for a cache-coherent interconnect memory expansion RP Kachare, J Lau, M Soltaniyeh, A Beygi, T Lac, D Subbanna, M Aghaee, ... US Patent App. 18/515,218, 2024 | | 2024 |
| Systems and methods for a cache-coherent interconnect protocol storage device RP Kachare, J Lau, A Beygi, M Soltaniyeh, T Lac, D Subbanna, M Aghaee, ... US Patent App. 18/513,496, 2024 | | 2024 |
| Near-storage format transformation M Soltaniyeh, X Yao, R Kachare US Patent App. 18/105,799, 2024 | | 2024 |
| Methods and system for importing data to a graph database using near-storage processing K Seongyoung, M Soltaniyeh, X Yao US Patent App. 18/456,955, 2024 | | 2024 |
| Systems and methods for near-storage processing in solid state drives M Soltaniyeh, VLM DOS REIS, M Bryson, X Yao US Patent App. 17/568,714, 2023 | | 2023 |
| Hardware-Software Techniques for Accelerating Sparse Computation M Soltaniyeh Rutgers The State University of New Jersey, School of Graduate Studies, 2022 | | 2022 |
| Boosting performance of directory-based cache coherence protocols by detecting private memory blocks at subpage granularity and using a low cost on-chip page table MR Soltaniyeh PQDT-Global, 2015 | | 2015 |
| A Scalable Cache Coherence Scheme for Large-Scale Chip Multiprocessor M Soltaniyeh ASPLOS SRC, 2015 | | 2015 |
