| SCNN: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH computer architecture news 45 (2), 27-40, 2017 | 1518 | 2017 |
| Timeloop: A systematic approach to dnn accelerator evaluation A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ... 2019 IEEE international symposium on performance analysis of systems and …, 2019 | 484 | 2019 |
| Sparse convolutional neural network accelerator WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison US Patent 10,891,538, 2021 | 408 | 2021 |
| Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach H Kwon, P Chatarasi, M Pellauer, A Parashar, V Sarkar, T Krishna Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 339 | 2019 |
| Sparse convolutional neural network accelerator WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison US Patent 10,528,864, 2020 | 308 | 2020 |
| Sparse convolutional neural network accelerator WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison US Patent 10,860,922, 2020 | 243 | 2020 |
| Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings H Kwon, P Chatarasi, V Sarkar, T Krishna, M Pellauer, A Parashar IEEE micro 40 (3), 20-29, 2020 | 201 | 2020 |
| Triggered instructions: A control paradigm for spatially-programmed architectures A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ... ACM SIGARCH Computer Architecture News 41 (3), 142-153, 2013 | 170 | 2013 |
| Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, and Joel Emer. 2019. Timeloop: A Systematic … A Parashar, P Raina 2019 IEEE international symposium on performance analysis of systems and …, 2019 | 162 | 2019 |
| HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing M Pellauer, M Adler, M Kinsy, A Parashar, J Emer 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 155 | 2011 |
| Leap scratchpads: automatic memory and cache management for reconfigurable logic M Adler, KE Fleming, A Parashar, M Pellauer, J Emer Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011 | 135 | 2011 |
| Mind mappings: enabling efficient algorithm-accelerator mapping space search K Hegde, PA Tsai, S Huang, V Chandra, A Parashar, CW Fletcher Proceedings of the 26th ACM International Conference on Architectural …, 2021 | 110 | 2021 |
| Mechanisms for bounding vulnerabilities of processor structures NK Soundararajan, A Parashar, A Sivasubramaniam Proceedings of the 34th annual international symposium on Computer …, 2007 | 82 | 2007 |
| Leveraging latency-insensitivity to ease multiple FPGA design KE Fleming, M Adler, M Pellauer, A Parashar, A Mithal, J Emer Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 77 | 2012 |
| SlicK: slice-based locality exploitation for efficient redundant multithreading A Parashar, A Sivasubramaniam, S Gurumurthi ACM SIGOPS Operating Systems Review 40 (5), 95-105, 2006 | 77 | 2006 |
| A complexity-effective approach to alu bandwidth enhancement for instruction-level temporal redundancy A Parashar, S Gurumurthi, A Sivasubramaniam ACM SIGARCH Computer Architecture News 32 (2), 376, 2004 | 72 | 2004 |
| Sparse convolutional neural network accelerator WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison US Patent 10,997,496, 2021 | 67 | 2021 |
| Sparseloop: An analytical approach to sparse tensor accelerator modeling YN Wu, PA Tsai, A Parashar, V Sze, JS Emer 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2022 | 63 | 2022 |
| Marvel: A data-centric approach for mapping deep learning operators on spatial accelerators P Chatarasi, H Kwon, A Parashar, M Pellauer, T Krishna, V Sarkar ACM Transactions on Architecture and Code Optimization (TACO) 19 (1), 1-26, 2021 | 56 | 2021 |
| Executing distributed memory operations using processing elements connected by distributed channels B Ahsan, MC Adler, NC Crago, JS Emer, A Jaleel, A Parashar, ... US Patent 10,331,583, 2019 | 56 | 2019 |
Joel EmerProfessor of the Practice, MIT - Sr. Distinguished Research Scientist, NvidiaEmail verificata su csail.mit.edu