28nm FDSOI technology platform for high-speed low-voltage digital applications N Planes, O Weber, V Barral, S Haendler, D Noblet, D Croain, M Bocat, ...
2012 Symposium on VLSI technology (VLSIT), 133-134, 2012
514 2012 Advances, challenges and opportunities in 3D CMOS sequential integration P Batude, M Vinet, B Previtali, C Tabone, C Xu, J Mazurier, O Weber, ...
2011 International Electron Devices Meeting, 7.3. 1-7.3. 4, 2011
419 2011 Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond O Faynot, F Andrieu, O Weber, C Fenouillet-Béranger, P Perreau, ...
2010 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2010
332 2010 Engineered substrates for future More Moore and More than Moore integrated devices L Clavelier, C Deguet, L Di Cioccio, E Augendre, A Brugere, P Gueguen, ...
2010 International Electron Devices Meeting, 2.6. 1-2.6. 4, 2010
284 2010 Multi- JP Noel, O Thomas, MA Jaud, O Weber, T Poiroux, C Fenouillet-Beranger, ...
IEEE Transactions on Electron Devices 58 (8), 2473-2482, 2011
235 2011 High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding O Weber, O Faynot, F Andrieu, C Buj-Dufournet, F Allain, P Scheiblin, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
206 2008 Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters M Cassé, L Thevenod, B Guillaumot, L Tosti, F Martin, J Mitard, O Weber, ...
IEEE Transactions on Electron Devices 53 (4), 759-768, 2006
195 2006 High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond Q Liu, M Vinet, J Gimbert, N Loubet, R Wacquez, L Grenouillet, Y Le Tiec, ...
2013 IEEE International Electron Devices Meeting, 9.2. 1-9.2. 4, 2013
125 2013 14nm FDSOI technology for high speed and energy efficient applications O Weber, E Josse, F Andrieu, A Cros, E Richard, P Perreau, E Baylac, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
117 2014 Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond F Andrieu, O Weber, J Mazurier, O Thomas, JP Noel, ...
2010 Symposium on VLSI Technology, 57-58, 2010
116 2010 Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below C Fenouillet-Beranger, P Perreau, S Denorme, L Tosti, F Andrieu, ...
2009 Proceedings of the European Solid State Device Research Conference, 89-92, 2009
105 2009 Truly innovative 28nm FDSOI technology for automotive micro-controller applications embedding 16MB phase change memory F Arnaud, P Zuliani, JP Reynard, A Gandolfo, F Disegni, P Mattavelli, ...
2018 IEEE International Electron Devices Meeting (IEDM), 18.4. 1-18.4. 4, 2018
92 2018 Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features TP Ernst, F Andrieu, O Weber, JM Hartmann, C Dupre, O Faynot, ...
ECS Transactions 3 (7), 947, 2006
90 2006 Strained tunnel FETs with record ION : first demonstration of ETSOI TFETs with SiGe channel and RSD A Villalon, C Le Royer, M Cassé, D Cooper, B Prévitali, C Tabone, ...
2012 Symposium on VLSI technology (VLSIT), 49-50, 2012
89 2012 Efficient multi-VT FDSOI technology with UTBOX for low power circuit design C Fenouillet-Beranger, O Thomas, P Perreau, JP Noel, A Bajolet, ...
2010 Symposium on VLSI Technology, 65-66, 2010
88 2010 On the variability in planar FDSOI technology: From MOSFETs to SRAM cells J Mazurier, O Weber, F Andrieu, A Toffoli, O Rozeau, T Poiroux, F Allain, ...
IEEE Transactions on electron devices 58 (8), 2326-2336, 2011
65 2011 Experimental and comparative investigation of low and high field transport in substrate-and process-induced strained nanoscaled MOSFETs F Andrieu, T Ernst, F Lime, F Rochette, K Romanjek, S Barraud, C Ravit, ...
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 176-177, 2005
64 2005 Hybrid FDSOI/Bulk high-k/Metal gate platform for Low Power (LP) multimedia technology C Fenouillet-Beranger, P Perreau, L Pham-Nguyen, S Denorme, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
61 2009 Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack O Weber, JF Damlencourt, F Andrieu, F Ducroquet, T Ernst, JM Hartmann, ...
IEEE transactions on electron devices 53 (3), 449-456, 2006
56 2006 Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS O Weber, Y Bogumilowicz, T Ernst, JM Hartmann, F Ducroquet, F Andrieu, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
56 2005 
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