| Tunnel junction engineering for optimized metallic single-electron transistor KG El Hajjam, MA Bounouar, N Baboux, S Ecoffey, M Guilmain, E Puyoo, ... IEEE Transactions on Electron Devices 62 (9), 2998-3003, 2015 | 15 | 2015 |
| Room temperature double gate single electron transistor based standard cell library MA Bounouar, A Beaumont, K El Hajjam, F Calmon, D Drouin Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale …, 2012 | 14 | 2012 |
| Single electron transistor analytical model for hybrid circuit design MA Bounouar, F Calmon, A Beaumont, M Guilmain, W Xuan, S Ecoffey, ... 2011 IEEE 9th International New Circuits and systems conference, 506-509, 2011 | 12 | 2011 |
| Recent developments on 3D integration of metallic set onto CMOS process for memory application N Jouvet, MA Bounouar, S Ecoffey, C Nauenheim, A Beaumont, ... International Journal of Nanoscience 11 (04), 1240024, 2012 | 10 | 2012 |
| On the use of nanoelectronic logic cells based on metallic Single Electron Transistors MA Bounouar, A Beaumont, F Calmon, D Drouin 2012 13th International Conference on Ultimate Integration on Silicon (ULIS …, 2012 | 8 | 2012 |
| Single electron CMOS-like one bit full adder D Griveau, S Ecoffey, RM Parekh, MA Bounouar, F Calmon, J Beauvais, ... 2012 13th International Conference on Ultimate Integration on Silicon (ULIS …, 2012 | 8 | 2012 |
| Towards nano-computing blocks using room temperature double-gate single electron transistors MA Bounouar, D Drouin, F Calmon 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS …, 2014 | 6 | 2014 |
| Double-gate single electron transistors: Modeling, design et evaluation of logic architectures MA Bounouar < bound method Organization. get_name_with_acronym of< Organization: TEL …, 2013 | 3 | 2013 |
| Transistors mono-electroniques double-grille: Modélisation, conception and évaluation d’architectures logiques MA Bounouar INSA de Lyon; Université de Sherbrooke (Québec, Canada), 2013 | 3 | 2013 |
| Static and Dynamic Modeling of Single-electron memory for circuit simulation W Xuan, A Beaumont, M Guilmain, MA Bounouar, N Baboux, J Etzkorn, ... IEEE transactions on electron devices 59 (1), 212-220, 2011 | 2 | 2011 |
| Double-Gate Single Electron Transistors: Modeling, Design & Evaluation of Logic Architectures Transistors Mono-Électroniques Double-Grille: Modélisation, Conception … MA BOUNOUAR | 1 | 2013 |
| Enhancing electrical performances of metallic DG-SET based circuits by tunnel junction engineering KG El Hajjam, MA Bounouar, D Drouin, F Calmon 2016 Joint International EUROSOI Workshop and International Conference on …, 2016 | | 2016 |
| 3D microelectronic with BEOL compatible devices D Drouin, MA Bounouar, G Droulers, M Labalette, M Pioro-Ladriere, ... VLSI Test Symposium (VTS), 2015 IEEE 33rd, 1-1, 2015 | | 2015 |
| Thermionic Emission filtering to increase SET operating temperature K El Hajjam, MA Bounouar, N Baboux, M Guilmain, E Puyoo¹, D Drouin, ... | | |
| Single Electron Device Model Library for Hybrid Circuit Design J Etzkorn, W Xuan, N Jouvet, A Beaumont, N Baboux, A Souifi, F Calmon, ... | | |
Dominique DrouinProfesseur Universite de SherbrookeEmail verificata su usherbrooke.ca
