| A multilayer neural accelerator with binary activations based on phase-change memory M Bertuletti, I Muñoz-Martín, S Bianchi, AG Bonfanti, D Ielmini IEEE Transactions on Electron Devices 70 (3), 986-992, 2023 | 12 | 2023 |
| Efficient parallelization of 5G-PUSCH on a scalable RISC-V many-core processor M Bertuletti, Y Zhang, A Vanelli-Coralli, L Benini 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 8 | 2023 |
| 3D partitioning with pipeline optimization for low-latency memory access in many-core SoCs S Das, S Riedel, M Bertuletti, L Benini, M Brunion, J Ryckaert, J Myers, ... 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2024 | 2 | 2024 |
| TeraPool-SDR: An 1.89 TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios Y Zhang, M Bertuletti, S Riedel, M Cavalcante, A Vanelli-Coralli, L Benini arXiv preprint arXiv:2405.04988, 2024 | 1 | 2024 |
| Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster M Bertuletti, S Riedel, Y Zhang, A Vanelli-Coralli, L Benini International Conference on Embedded Computer Systems, 241-254, 2023 | 1 | 2023 |
| TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs D Shen, Y Zhang, M Bertuletti, L Benini arXiv preprint arXiv:2501.14370, 2025 | | 2025 |
| Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC S Das, S Riedel, M Naeim, M Brunion, M Bertuletti, L Benini, J Ryckaert, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024 | | 2024 |
| A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR Y Zhang, M Bertuletti, C Zhang, S Riedel, A Vanelli-Coralli, L Benini arXiv preprint arXiv:2408.08882, 2024 | | 2024 |
| A multi-layer hardware neural accelerator based on phase-change memory synapses for efficient in-memory computing M Bertuletti | | 2020 |
Luca BeniniETH Zürich, Università di BolognaEmail verificata su unibo.it