How to control solid state dewetting: A short review F Leroy, F Cheynis, Y Almadori, S Curiotto, M Trautmann, JC Barbé, ...
Surface Science Reports 71 (2), 391-409, 2016
235 2016 Performance and design considerations for gate-all-around stacked-NanoWires FETs S Barraud, V Lapras, B Previtali, MP Samson, J Lacord, S Martinie, ...
2017 IEEE international electron devices meeting (IEDM), 29.2. 1-29.2. 4, 2017
150 2017 Surface diffusion dewetting of thin solid films: Numerical method and application to E Dornel, JC Barbe, F De Crécy, G Lacolle, J Eymery
Physical Review B—Condensed Matter and Materials Physics 73 (11), 115427, 2006
137 2006 Challenges for 3D IC integration: bonding quality and thermal management P Leduc, F de Crecy, M Fayolle, B Charlet, T Enot, M Zussy, B Jones, ...
2007 IEEE International Interconnect Technology Conferencee, 210-212, 2007
124 2007 Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack T Ernst, C Dupre, C Isheden, E Bernard, R Ritzenthaler, V Maffini-Alvaro, ...
2006 International Electron Devices Meeting, 1-4, 2006
97 2006 Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features TP Ernst, F Andrieu, O Weber, JM Hartmann, C Dupre, O Faynot, ...
ECS Transactions 3 (7), 947, 2006
90 2006 Computer simulation of the microstructure and rheology of semi-solid alloys under shear M Perez, JC Barbé, Z Neda, Y Bréchet, L Salvo
Acta materialia 48 (14), 3773-3782, 2000
75 2000 Leti-UTSOI2. 1: A compact model for UTBB-FDSOI technologies—Part I: Interface potentials analytical model T Poiroux, O Rozeau, P Scheer, S Martinie, MA Jaud, M Minondo, A Juge, ...
IEEE Transactions on Electron Devices 62 (9), 2751-2759, 2015
65 2015 Leti-UTSOI2. 1: A compact model for UTBB-FDSOI technologies—Part II: DC and AC model description T Poiroux, O Rozeau, P Scheer, S Martinie, MA Jaud, M Minondo, A Juge, ...
IEEE Transactions on Electron Devices 62 (9), 2760-2768, 2015
64 2015 Undulation of sub-100nm porous dielectric structures: A mechanical analysis M Darnon, T Chevolleau, O Joubert, S Maitrejean, JC Barbe, J Torres
Applied Physics Letters 91 (19), 2007
63 2007 Hydrogen annealing of arrays of planar and vertically stacked Si nanowires E Dornel, T Ernst, JC Barbé, JM Hartmann, V Delaye, F Aussenac, ...
Applied Physics Letters 91 (23), 2007
60 2007 A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters S Cristoloveanu, KH Lee, MS Parihar, H El Dirani, J Lacord, S Martinie, ...
Solid-State Electronics 143, 10-19, 2018
59 2018 Extended Analysis of the C Navarro, J Lacord, MS Parihar, F Adamu-Lema, M Duan, N Rodriguez, ...
IEEE Transactions on Electron Devices 64 (11), 4486-4491, 2017
46 2017 25nm Short and narrow strained FDSOI with TiN/HfO2 gate stack S Deleonibus, C Mazure, P Gaud, H Grampeix, JP Colonna, B Previtali, ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 134-135, 2006
45 2006 Comparative scalability of PVD and CVD TiN on HfO2 as a metal gate stack for FDSOI cMOSFETs down to 25nm gate length and width F Andrieu, O Faynot, X Garros, D Lafond, C Buj-Dufournet, L Tosti, ...
2006 International Electron Devices Meeting, 1-4, 2006
43 2006 UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs T Poiroux, O Rozeau, S Martinie, P Scheer, S Puget, MA Jaud, S El Ghouli, ...
2013 IEEE International Electron Devices Meeting, 12.4. 1-12.4. 4, 2013
37 2013 C Navarro, M Duan, MS Parihar, F Adamu-Lema, S Coseman, J Lacord, ...
IEEE Transactions on Electron Devices 64 (12), 4904-4909, 2017
35 2017 Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of< 100> or< 110> oriented FDSOI cMOSFETs for the 32nm Node F Andrieu, O Faynot, F Rochette, JC Barbé, C Buj, Y Bogumilowicz, ...
2007 IEEE Symposium on VLSI Technology, 50-51, 2007
31 2007 A comprehensive model on field-effect pnpn devices (Z2-FET) Y Taur, J Lacord, MS Parihar, J Wan, S Martinie, K Lee, M Bawedin, ...
Solid-State Electronics 134, 1-8, 2017
23 2017 Parasitic capacitance analytical model for sub-7-nm multigate devices J Lacord, S Martinie, O Rozeau, MA Jaud, S Barraud, JC Barbé
IEEE Transactions on Electron Devices 63 (2), 781-786, 2015
23 2015 