Wireless communication technology, apparatuses, and methods E Alpman, AL Amadjikpe, O Asaf, K Azadet, R Banin, M Baryakh, A Bazov, ...
US Patent 11,424,539, 2022
306 2022 An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes BK Casper, M Haycock, R Mooney
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 2002
304 2002 A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS G Balamurugan, J Kennedy, G Banerjee, JE Jaussi, M Mansuri, ...
IEEE Journal of Solid-State Circuits 43 (4), 1010-1019, 2008
211 2008 Differential amplifier offset adjustment BK Casper, JE Jaussi
US Patent 6,614,301, 2003
162 2003 8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew JE Jaussi, G Balamurugan, DR Johnson, B Casper, A Martin, J Kennedy, ...
IEEE Journal of Solid-State Circuits 40 (1), 80-88, 2005
150 2005 Clocking analysis, implementation and measurement techniques for high-speed data links—A tutorial B Casper, F O'Mahony
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (1), 17-39, 2009
147 2009 Systems, methods, and apparatuses for stacked memory B Casper, R Mooney, D Dunning, M Mansuri, JE Jaussi
US Patent 8,612,809, 2013
143 2013 Wireline receiver circuitry having collaborative timing recovery T Musah, G Keskin, G Balamurugan, JE Jaussi, BK Casper
US Patent 9,374,250, 2016
121 2016 Modeling and analysis of high-speed I/O links G Balamurugan, B Casper, JE Jaussi, M Mansuri, F O'Mahony, J Kennedy
IEEE transactions on advanced packaging 32 (2), 237-247, 2009
118 2009 A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B. B Casper, J Jaussi, F O'Mahony, M Mansuri, K Canagasaby, J Kennedy, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
118 * 2006 An 8-Gb/s simultaneous bidirectional link with on-die waveform capture B Casper, A Martin, JE Jaussi, J Kennedy, R Mooney
IEEE Journal of Solid-State Circuits 38 (12), 2111-2120, 2003
116 2003 A scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-lane parallel I/O in 32-nm CMOS M Mansuri, JE Jaussi, JT Kennedy, TC Hsueh, S Shekhar, ...
IEEE Journal of solid-state circuits 48 (12), 3229-3242, 2013
114 2013 A 47 F O'Mahony, JE Jaussi, J Kennedy, G Balamurugan, M Mansuri, ...
IEEE journal of solid-state circuits 45 (12), 2828-2837, 2010
113 2010 A 3-D-integrated silicon photonic microring-based 112-Gb/s PAM-4 transmitter with nonlinear equalization and thermal control H Li, G Balamurugan, T Kim, MN Sakib, R Kumar, H Rong, J Jaussi, ...
IEEE Journal of Solid-State Circuits 56 (1), 19-29, 2020
90 2020 Strong Injection Locking in Low- S Shekhar, M Mansuri, F O'Mahony, G Balamurugan, JE Jaussi, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (8), 1818-1829, 2009
87 2009 A 112 Gb/s PAM4 silicon photonics transmitter with microring modulator and CMOS driver H Li, G Balamurugan, M Sakib, J Sun, J Driscoll, R Kumar, H Jayatilleka, ...
Journal of Lightwave Technology 38 (1), 131-138, 2020
86 2020 Clock recovery apparatus, method, and system BK Casper, AK Martin, SR Mooney, JE Jaussi
US Patent 7,457,393, 2008
80 2008 Future microprocessor interfaces: Analysis, design and optimization B Casper, G Balamurugan, JE Jaussi, J Kennedy, M Mansuri, F O'Mahony, ...
2007 IEEE Custom Integrated Circuits Conference, 479-486, 2007
76 2007 A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS H Li, G Balamurugan, J Jaussi, B Casper
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018
73 2018 Filtering variable offset amplifier JE Jaussi, BK Casper, AK Martin
US Patent 7,301,391, 2007
72 2007 
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