| Timeloop: A Systematic Approach to DNN Accelerator Evaluation A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ... International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019 | 484 | 2019 |
| Simba: Scaling deep-learning inference with multi-chip-module-based architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 470 | 2019 |
| Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures YS Shao, B Reagen, GY Wei, D Brooks International Symposium on Computer Architecture (ISCA), 2014 | 416 | 2014 |
| MachSuite: Benchmarks for Accelerator Design and Customized Architectures B Reagen, R Adolf, YS Shao, GY Wei, D Brooks IEEE International Symposium on Workload Characterization (IISWC), 2014 | 350 | 2014 |
| Chipyard: Integrated design, simulation, and implementation framework for custom socs A Amid, D Biancolin, A Gonzalez, D Grubb, S Karandikar, H Liew, ... IEEE Micro 40 (4), 10-21, 2020 | 338 | 2020 |
| Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration H Genc, S Kim, A Amid, A Haj-Ali, V Iyer, P Prakash, J Zhao, D Grubb, ... Design Automation Conference (DAC), 2021 | 264 | 2021 |
| Co-Designing Accelerators and SoC Interfaces using gem5-Aladdin YS Shao, SL Xi, V Srinivasan, GY Wei, D Brooks International Symposium on Microarchitecture (MICRO), 2016 | 219 | 2016 |
| Energy Characterization and Instruction-Level Energy Model of Intel’s Xeon Phi Processor YS Shao, D Brooks International Symposium on Low Power Electronics and Design (ISLPED), 2013 | 188 | 2013 |
| Magnet: A modular accelerator generator for neural networks R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 140 | 2019 |
| Neurovectorizer: End-to-end vectorization with deep reinforcement learning A Haj-Ali, NK Ahmed, T Willke, YS Shao, K Asanovic, I Stoica Proceedings of the 18th ACM/IEEE International Symposium on Code Generation …, 2020 | 132 | 2020 |
| CoSA: Scheduling by Constrained Optimization for Spatial Accelerators Q Huang, M Kang, G Dinh, T Norell, A Kalaiah, J Demmel, J Wawrzynek, ... International Symposium on Computer Architecture (ISCA), 2021 | 131 | 2021 |
| A 0.32–128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020 | 113 | 2020 |
| Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning architectures H Genc, A Haj-Ali, V Iyer, A Amid, H Mao, J Wright, C Schmidt, J Zhao, ... arXiv preprint arXiv:1911.09925 3 (25), 15-17, 2019 | 110 | 2019 |
| ISA-Independent Workload Characterization and its Implications for Specialized Architectures YS Shao, D Brooks International Symposium on Performance Analysis of Systems and Software …, 2013 | 99 | 2013 |
| Full stack optimization of transformer inference: a survey S Kim, C Hooper, T Wattanawong, M Kang, R Yan, H Genc, G Dinh, ... arXiv preprint arXiv:2302.14017, 2023 | 95 | 2023 |
| A modular digital VLSI flow for high-productivity SoC design B Khailany, E Khmer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ... Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 76 | 2018 |
| SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference JF Zhang, CE Lee, C Liu, YS Shao, SW Keckler, Z Zhang IEEE Journal of Solid-State Circuits, 2020 | 75 | 2020 |
| Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration M Pellauer, YS Shao, J Clemons, N Crago, K Hegde, R Ventakesan, ... International Conference on Architectural Support for Programming Languages …, 2019 | 73 | 2019 |
| The Aladdin Approach to Accelerator Design and Modeling YS Shao, B Reagen, GY Wei, D Brooks IEEE Micro, 2015 | 61 | 2015 |
| A 0.11 pj/op, 0.32-128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... 2019 Symposium on VLSI Circuits, C300-C301, 2019 | 56 | 2019 |
Steve KecklerVice President of Architecture Research, NVIDIAEmail verificata su cs.utexas.edu