| Energy-efficient mechanisms for managing thread context in throughput processors M Gebhart, DR Johnson, D Tarjan, SW Keckler, WJ Dally, E Lindholm, ... Proceedings of the 38th annual international symposium on Computer …, 2011 | 354 | 2011 |
| Rigel: An architecture and scalable programming interface for a 1000-core accelerator JH Kelm, DR Johnson, MR Johnson, NC Crago, W Tuohy, A Mahesri, ... Proceedings of the 36th annual international symposium on Computer …, 2009 | 206 | 2009 |
| Goldmine: Automatic assertion generation using data mining and static analysis S Vasudevan, D Sheridan, S Patel, D Tcheng, B Tuohy, D Johnson 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 201 | 2010 |
| Scaling the power wall: a path to exascale O Villa, DR Johnson, M Oconnor, E Bolotin, D Nellans, J Luitjens, ... SC'14: Proceedings of the International Conference for High Performance …, 2014 | 187 | 2014 |
| Flexible software profiling of gpu architectures M Stephenson, SK Sastry Hari, Y Lee, E Ebrahimi, DR Johnson, ... Proceedings of the 42nd Annual International Symposium on Computer …, 2015 | 136 | 2015 |
| Architecting an energy-efficient dram system for gpus N Chatterjee, M O’Connor, D Lee, DR Johnson, SW Keckler, M Rhu, ... 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 120 | 2017 |
| Priority-based cache allocation in throughput processors D Li, M Rhu, DR Johnson, M O'Connor, M Erez, D Burger, DS Fussell, ... 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 120 | 2015 |
| Cohesion: a hybrid memory model for accelerators JH Kelm, DR Johnson, W Tuohy, SS Lumetta, SJ Patel Proceedings of the 37th annual international symposium on Computer …, 2010 | 73 | 2010 |
| A variable warp size architecture TG Rogers, DR Johnson, M O'Connor, SW Keckler ACM SIGARCH Computer Architecture News 43 (3S), 489-501, 2015 | 63 | 2015 |
| Two-level scheduler for multi-threaded processing WJ Dally, SW Keckler, D Tarjan, JE Lindholm, MA Gebhart, DR Johnson US Patent 8,732,711, 2014 | 61 | 2014 |
| A hierarchical thread scheduler and register file for energy-efficient throughput processors M Gebhart, DR Johnson, D Tarjan, SW Keckler, WJ Dally, E Lindholm, ... ACM Transactions on Computer Systems (TOCS) 30 (2), 1-38, 2012 | 58 | 2012 |
| Tradeoffs in designing accelerator architectures for visual computing A Mahesri, D Johnson, N Crago, SJ Patel 2008 41st IEEE/ACM International Symposium on Microarchitecture, 164-175, 2008 | 57 | 2008 |
| Rigel: A 1,024-core single-chip accelerator architecture D Johnson, M Johnson, J Kelm, W Tuohy, S Lumetta, S Patel IEEE Micro 31 (4), 30-41, 2011 | 51 | 2011 |
| Cohesion: An adaptive hybrid memory model for accelerators JH Kelm, DR Johnson, W Tuohy, SS Lumetta, SJ Patel IEEE micro 31 (1), 42-55, 2011 | 42 | 2011 |
| A task-centric memory model for scalable accelerator architectures JH Kelm, DR Johnson, SS Lumetta, MI Frank, SJ Patel 2009 18th International Conference on Parallel Architectures and Compilation …, 2009 | 33 | 2009 |
| Patch memory system JL Clemons, CC Cheng, DR Johnson, SW Keckler, I Frosio, T Yun-Ta US Patent 9,934,153, 2018 | 28 | 2018 |
| A patch memory system for image processing and computer vision J Clemons, CC Cheng, I Frosio, D Johnson, SW Keckler 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 27 | 2016 |
| System, method, and computer program product for prioritized access for multithreaded processing DR Johnson, M Rhu, JM O'Connor, SW Keckler US Patent App. 14/147,395, 2015 | 23 | 2015 |
| Pitfalls of orion-based simulation M Hayenga, DR Johnson, M Lipasti ORION 35, 40-000, 2010 | 18 | 2010 |
| Speculative reconvergence for improved SIMT efficiency S Damani, DR Johnson, M Stephenson, SW Keckler, E Yan, M McKeown, ... Proceedings of the 18th ACM/IEEE International Symposium on Code Generation …, 2020 | 15 | 2020 |
Steve KecklerVice President of Architecture Research, NVIDIAEmail verificata su cs.utexas.edu
