| Design and optimization of residual neural network accelerators for low-power fpgas using high-level synthesis F Minnella, T Urso, MT Lazarescu, L Lavagno arXiv preprint arXiv:2309.15631, 2023 | 6 | 2023 |
| Protection and characterization of an open source soft core against radiation effects F Minnella Politecnico di Torino, 2018 | 6 | 2018 |
| Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops F Minnella, J Cortadella, MR Casu, MT Lazarescu, L Lavagno IEEE access 11, 35830-35840, 2023 | 4 | 2023 |
| Control circuit for a multiphase buck converter, related integrated circuit, multiphase buck converter and method of operating a multiphase buck converter G Castellano, L Pedone, F Minnella, M Raimondi US Patent 12,021,454, 2024 | 2 | 2024 |
| NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming R Bosio, F Minnella, T Urso, MR Casu, L Lavagno, MT Lazarescu, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 1 | 2024 |
| LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA R Bosio, G Brignone, F Minnella, MU Jamal, L Lavagno 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-2, 2024 | 1 | 2024 |
| Processing system, related integrated circuit, system and method F Minnella, G Donzelli US Patent 12,056,074, 2024 | | 2024 |
| Mix & Latch: High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops F Minnella Politecnico di Torino, 2024 | | 2024 |
| Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark L Lagostina, F Minnella, J Cortadella, MR Casu, MT Lazarescu, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2024 | | 2024 |
| Electronic device comprising a memory accessible via a JTAG interface, and corresponding method of accessing a memory F Minnella US Patent 11,789,078, 2023 | | 2023 |
