| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 Symposium on VLSI Technology, T230-T231, 2017 | 980 | 2017 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE International Electron Devices Meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 193 | 2016 |
| Nanosheet MOSFET with full-height air-gap spacer K Cheng, BB Doris, MA Guillorn, X Miao US Patent 9,362,355, 2016 | 143 | 2016 |
| Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ... 2018 IEEE International Electron Devices Meeting (IEDM), 28.6. 1-28.6. 4, 2018 | 93 | 2018 |
| A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices N Loubet, S Kal, C Alix, S Pancharatnam, H Zhou, C Durfee, M Belyansky, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.4. 1-11.4. 4, 2019 | 81 | 2019 |
| Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019 | 81 | 2019 |
| Site-controlled VLS Growth of Planar Nanowires: Yield and Mechanism C Zhang, X Miao, PK Mohseni, W Choi, X Li Nano letters 14 (12), 6836-6841, 2014 | 79 | 2014 |
| High-speed planar GaAs nanowire arrays with fmax> 75 GHz by wafer-scale bottom-up growth X Miao, K Chabak, C Zhang, P Katal Mohseni, D Walker Jr, X Li Nano letters, 2014 | 69 | 2014 |
| High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor J Zhang, T Ando, CW Yeung, M Wang, O Kwon, R Galatage, R Chao, ... 2017 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2017 | 64 | 2017 |
| Stacked nanowires Z Bi, K Cheng, J Li, X Miao US Patent 9,716,142, 2017 | 63 | 2017 |
| Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer BB Doris, MA Guillorn, I Lauer, X Miao US Patent 9,647,139, 2017 | 63 | 2017 |
| Air gap spacer between contact and gate region K Cheng, NJ Loubet, X Miao, A Reznicek US Patent 9,716,158, 2017 | 62 | 2017 |
| Gate length controlled vertical FETs K Cheng, X Miao, XU Wenyu, C Zhang US Patent 10,153,367, 2018 | 60 | 2018 |
| Air spacer for 10nm FinFET CMOS and beyond K Cheng, C Park, C Yeung, S Nguyen, J Zhang, X Miao, M Wang, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.1. 1-17.1. 4, 2016 | 60 | 2016 |
| Fabrication of a vertical transistor with self-aligned bottom source/drain K Cheng, X Miao, XU Wenyu, C Zhang US Patent 10,083,871, 2018 | 49 | 2018 |
| Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology YM Lee, MH Na, A Chu, A Young, T Hook, L Liebmann, EJ Nowak, ... 2017 IEEE International Electron Devices Meeting (IEDM), 29.3. 1-29.3. 4, 2017 | 48 | 2017 |
| Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure BB Doris, MA Guillorn, I Lauer, X Miao US Patent 9,911,592, 2018 | 44 | 2018 |
| FinFET performance with Si: P and Ge: Group-III-metal metastable contact trench alloys O Gluschenkov, Z Liu, H Niimi, S Mochizuki, J Fronheiser, X Miao, J Li, ... Electron Devices Meeting (IEDM), 2016 IEEE International, 17.2. 1-17.2. 4, 2016 | 44 | 2016 |
| Width adjustment of stacked nanowires K Cheng, X Miao, R Xie, T Yamashita US Patent 10,069,015, 2018 | 43 | 2018 |
| Monolithic barrier-all-around high electron mobility transistor with planar GaAs nanowire channel X Miao, C Zhang, X Li Nano letters 13 (6), 2548-2552, 2013 | 43 | 2013 |
Chen ZhangIBM ResearchEmail verificata su us.ibm.com