עקוב אחר
Luca Sterpone
Luca Sterpone
כתובת אימייל מאומתת בדומיין polito.it
כותרת
צוטט על ידי
צוטט על ידי
שנה
Microvesicles derived from adult human bone marrow and tissue specific mesenchymal stem cells shuttle selected pattern of miRNAs
F Collino, MC Deregibus, S Bruno, L Sterpone, G Aghemo, L Viltono, ...
PloS one 5 (7), e11803, 2010
7542010
On the optimal design of triple modular redundancy logic for SRAM-based FPGAs
FL Kastensmidt, L Sterpone, L Carro, MS Reorda
Design, Automation and Test in Europe, 1290-1295, 2005
3232005
A new reliability-oriented place and route algorithm for SRAM-based FPGAs
L Sterpone, M Violante
IEEE Transactions on Computers 55 (6), 732-744, 2006
2052006
Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
L Sterpone, M Violante
IEEE Transactions on Nuclear Science 52 (5), 1545-1549, 2005
1762005
A new partial reconfiguration-based fault-injection system to evaluate SEU effects in SRAM-based FPGAs
L Sterpone, M Violante
IEEE Transactions on Nuclear Science 54 (4), 965-970, 2007
1532007
A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs
L Sterpone, M Violante
IEEE Transactions on Nuclear Science 52 (6), 2217-2223, 2005
1252005
Using benchmarks for radiation testing of microprocessors and FPGAs
H Quinn, WH Robinson, P Rech, M Aguirre, A Barnard, M Desogus, ...
IEEE transactions on nuclear science 62 (6), 2547-2554, 2015
1232015
A new hardware/software platform and a new 1/E neutron source for soft error studies: Testing FPGAs at the ISIS facility
M Violante, L Sterpone, A Manuzzato, S Gerardin, P Rech, M Bagatin, ...
IEEE Transactions on Nuclear Science 54 (4), 1184-1189, 2007
1072007
On the evaluation of SEU sensitiveness in SRAM-based FPGAs
P Bernardi, MS Reorda, L Sterpone, M Violante
Proceedings. 10th IEEE International On-Line Testing Symposium, 115-120, 2004
832004
Reconfigurable field programmable gate arrays for mission-critical applications
N Battezzati, L Sterpone, M Violante
Springer Science & Business Media, 2010
762010
Simulation-based analysis of SEU effects in SRAM-based FPGAs
M Violante, L Sterpone, M Ceschia, D Bortolato, P Bernardi, MS Reorda, ...
IEEE Transactions on Nuclear Science 51 (6), 3354-3359, 2004
722004
FlexGripPlus: An improved GPGPU model to support reliability analysis
JER Condia, B Du, MS Reorda, L Sterpone
Microelectronics Reliability 109, 113660, 2020
692020
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
F Abate, L Sterpone, CA Lisboa, L Carro, M Violante
IEEE Transactions on Nuclear Science 56 (4), 1992-2000, 2009
662009
Analysis of set propagation in flash-based fpgas by means of electrical pulse injection
L Sterpone, N Battezzati, V Ferlet-Cavrois
IEEE Transactions on Nuclear Science 57 (4), 1820-1826, 2010
642010
FPGAs and parallel architectures for aerospace applications
F Kastensmidt, P Rech
Soft errors and fault-tolerant design, 2016
612016
An error-detection and self-repairing method for dynamically and partially reconfigurable systems
MS Reorda, L Sterpone, A Ullah
IEEE Transactions on Computers 66 (6), 1022-1033, 2016
602016
An analytical model of the propagation induced pulse broadening (PIPB) effects on single event transient in flash-based FPGAs
L Sterpone, N Battezzati, FL Kastensmidt, R Chipana
IEEE Transactions on Nuclear science 58 (5), 2333-2340, 2011
602011
A novel fault tolerant and runtime reconfigurable platform for satellite payload processing
L Sterpone, M Porrmann, J Hagemeyer
IEEE transactions on computers 62 (8), 1508-1525, 2013
592013
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
MS Reorda, L Sterpone, M Violante
European Test Symposium (ETS'05), 136-141, 2005
532005
Ultrahigh energy heavy ion test beam on Xilinx Kintex-7 SRAM-based FPGA
B Du, L Sterpone, S Azimi, DM Codinachs, V Ferlet-Cavrois, CB Polo, ...
IEEE Transactions on Nuclear Science 66 (7), 1813-1819, 2019
492019
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מאמרים 1–20