| Multiplier design utilizing Tri valued logic for RLNS based DSP RV Shalini, P Sampath Circuits and Systems 7 (4), 417-433, 2016 | 3 | 2016 |
| Multiplier design incorporating logarithmic number system for residue number system in binary logic RV Shalini, P Sampath Int. J. VLSI Signal Process 5 (3), 10-21, 2018 | 2 | 2018 |
| Multiplier design utilizing tri valued logic for RLNS based DSP applications SR Valliammal, S Palaniswami Circuits and Systems 7 (4), 417-433, 2016 | 2 | 2016 |
| Enhanced Quasi-Static Energy Recovery and Modified Clock Gating for the Wallace Tree Multiplier with Reversible Adders RV Shalini IETE Journal of Research, 1-14, 2023 | 1 | 2023 |
| Designing of Area and Power Efficient Modulo 2N Multiplier RV Shalini, P Sampath 2014 3rd International Conference on Eco-friendly Computing and …, 2014 | 1 | 2014 |
| Performing Template Matching Process for RLNS Based System in Binary Logic RV Shalini BP International, 2021 | | 2021 |
| Novel Idea of Implementing MRNS Technique for RLNS Based System RV Shalini BP International, 2021 | | 2021 |
| Design of Ternary Logic Logarithmic Conversion Circuit with Error Correction Technique RV Shalini, P Sampath Solid State Technology 64 (2), 1121-1142, 2021 | | 2021 |
| OPERAND DECOMPOSITION TECHNIQUE BASED LOGARITHMIC MULTIPLIERS FOR BOTH BINARY AND TERNARY LOGIC RV Shalini, P Sampath | | |
