TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing J Constantin, A Dogan, O Andersson, P Meinerzhagen, JN Rodrigues, ... 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012 | 48 | 2012 |
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS P Meinerzhagen, O Andersson, B Mohammadi, Y Sherazi, A Burg, ... 2012 Proceedings of the ESSCIRC (ESSCIRC), 321-324, 2012 | 42 | 2012 |
A 128 kb 7T SRAM using a single-cycle boosting mechanism in 28-nm FD–SOI B Mohammadi, O Andersson, J Nguyen, L Ciampolini, A Cathelin, ... IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1257-1268, 2017 | 29 | 2017 |
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS O Andersson, B Mohammadi, P Meinerzhagen, A Burg, J Rodrigues IEEE Transactions on Circuits and Systems I: Regular Papers, 2016 | 29 | 2016 |
A 290 mV Sub- ASIC for Real-Time Atrial Fibrillation Detection O Andersson, KH Chon, L Sornmo, JN Rodrigues IEEE, 2014 | 28 | 2014 |
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS O Andersson, B Mohammadi, P Meinerzhagen, A Burg, JN Rodrigues 2013 Proceedings of the ESSCIRC (ESSCIRC), 197-200, 2013 | 22 | 2013 |
A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS O Andersson, B Mohammadi, P Meinerzhagen, J Rodrigues ESSCIRC, 2014 | 16 | 2014 |
Improving Practical Sensitivity of Energy Optimized Wake-Up Receivers: Proof of Concept in 65-nm CMOS NS Mazloum, JN Rodrigues, O Andersson, A Nejdel, O Edfors IEEE Sensors Journal 16 (22), 8158-8166, 2016 | 13 | 2016 |
Synthesis strategies for sub-VT systems P Meinerzhagen, O Andersson, Y Sherazi, A Burg, J Rodrigues 2011 20th European Conference on Circuit Theory and Design (ECCTD), 552-555, 2011 | 10 | 2011 |
65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography S Asif, O Andersson, J Rodrigues, Y Kong IET Computers & Digital Techniques 12 (2), 62-67, 2018 | 8 | 2018 |
A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3 V 7T sense-amplifierless SRAM in 28 nm FD-SOI B Mohammadi, O Andersson, J Nguyen, L Ciampolini, A Cathelin, ... ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 429-432, 2016 | 8 | 2016 |
IR-drop reduction in sub-VT circuits by de-synchronization A Karlsson, O Andersson, J Sparsø, JN Rodrigues 2012 IEEE Subthreshold Microelectronics Conference (SubVT), 1-3, 2012 | 6 | 2012 |
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS B Mohammadi, O Andersson, P Meinerzhagen, Y Sherazi, A Burg, ... FTFC, 2014 | 4 | 2014 |
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing J Constantin, A Dogan, O Andersson, P Meinerzhagen, J Rodrigues, ... VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design: 20th IFIP …, 2013 | 4 | 2013 |
Impact of switching activity on the energy minimum voltage for 65 nm sub-VTCMOS O Andersson, SMY Sherazi, JN Rodrigues 2011 NORCHIP, 1-4, 2011 | 4 | 2011 |
A neural network engine for resource constrained embedded systems Z Jelčicová, A Mardari, O Andersson, E Kasapaki, J Sparsø 2020 54th Asilomar Conference on Signals, Systems, and Computers, 125-131, 2020 | 3 | 2020 |
Ultra-low Voltage Embedded Memories–Design Aspects and a Biomedical Use-case O Andersson Department of Electrical and Information Technology, Lund University, 2016 | 2 | 2016 |
An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI B Mohammadi, O Andersson, X Luo, M Nouripayam, JN Rodrigues 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 229-232, 2016 | 1 | 2016 |
A Wide-Operating Range Standard-Cell Based Memory in 28nm FD-SOI O Andersson, B Mohammadi, JN Rodrigues | 1 | 2016 |
A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS O Andersson, JN Rodrigues 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2628-2631, 2015 | 1 | 2015 |