| Impact of process-variations in STTRAM and adaptive boosting for robustness S Motaman, S Ghosh, N Rathi 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 60 | 2015 |
| A novel slope detection technique for robust STTRAM sensing S Motaman, S Ghosh, JP Kulkarni 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 30 | 2015 |
| Domain wall memory-layout, circuit and synergistic systems S Motaman, AS Iyengar, S Ghosh IEEE Transactions on Nanotechnology 14 (2), 282-291, 2015 | 30 | 2015 |
| Synergistic circuit and system design for energy-efficient and robust domain wall caches S Motaman, A Iyengar, S Ghosh Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 27 | 2014 |
| A perspective on test methodologies for supervised machine learning accelerators S Motaman, S Ghosh, J Park IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (3 …, 2019 | 14 | 2019 |
| Adaptive write and shift current modulation for process variation tolerance in domain wall caches S Motaman, S Ghosh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (3), 944-953, 2015 | 14 | 2015 |
| Dynamic computing in memory (DCIM) in resistive crossbar arrays S Motaman, S Ghosh 2018 IEEE 36th International Conference on Computer Design (ICCD), 179-186, 2018 | 13 | 2018 |
| Overview of circuits, systems, and applications of spintronics S Ghosh, A Iyengar, S Motaman, R Govindaraj, JW Jang, J Chung, J Park, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (3 …, 2016 | 13 | 2016 |
| Threshold defined camouflaged gates in 65nm technology for reverse engineering protection AS Iyengar, D Vontela, I Reddy, S Ghosh, S Motaman, J Jang Proceedings of the International Symposium on Low Power Electronics and …, 2018 | 12 | 2018 |
| Cache bypassing and checkpointing to circumvent data security attacks on STTRAM S Motaman, S Ghosh, N Rathi IEEE Transactions on Emerging Topics in Computing 7 (2), 262-270, 2017 | 7 | 2017 |
| VFAB: A novel 2-stage STTRAM sensing using voltage feedback and boosting S Motaman, S Ghosh, JP Kulkarni IEEE Transactions on Circuits and Systems I: Regular Papers 65 (6), 1919-1928, 2017 | 6 | 2017 |
| Simultaneous sizing, reference voltage and clamp voltage biasing for robustness, self-calibration and testability of STTRAM arrays S Motaman, S Ghosh Proceedings of the 51st Annual Design Automation Conference, 1-2, 2014 | 6 | 2014 |
| Novel application of spintronics in computing, sensing, storage and cybersecurity S Motaman, MNI Khan, S Ghosh 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 125-130, 2018 | 5 | 2018 |
| Addressing resiliency of in-memory floating point computation SS Ensan, S Ghosh, S Motaman, D Weast IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (9 …, 2022 | 1 | 2022 |
| A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays S Motaman, S Ghosh, JW Jang, A Iyengar, R Govindaraj, Z Khondker arXiv preprint arXiv:2306.03972, 2023 | | 2023 |
| Addressing Resiliency of In-Memory Floating Point Computation S Sayyah Ensan, S Ghosh, S Motaman, D Weast arXiv e-prints, arXiv: 2011.00648, 2020 | | 2020 |
| Low Power, Secure and Robust Designs of Non-volatile Memories S Motaman The Pennsylvania State University, 2018 | | 2018 |
| Robust slope detection technique for STTRAM and MRAM sensing S Ghosh, S Motaman US Patent 9,818,466, 2017 | | 2017 |
| Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing S Motaman, S Ghosh, J Kulkarni Journal on Emerging Technologies in Computing Systems (JETC) 14 (1), 8, 2017 | | 2017 |
| Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems........... J. Lee and S. Kim 871 Designing Tunable Subthreshold Logic Circuits Using Adaptive … M Zangeneh, A Joshi, EP Kim, J Choi, NR Shanbhag, RA Rutenbar, ... | | |
Swaroop GhoshPennsylvania State Universityכתובת אימייל מאומתת בדומיין psu.edu