| A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans S Dupuis, PS Ba, G Di Natale, ML Flottes, B Rouzeyre 2014 IEEE 20th International Symposium on On-Line Testing and Robust System …, 2014 | 299 | 2014 |
| A survey on simulation-based fault injection tools for complex systems M Kooli, G Di Natale 2014 9th IEEE International Conference on Design & Technology of Integrated …, 2014 | 146 | 2014 |
| Test versus security: Past and present J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede IEEE Transactions on Emerging topics in Computing 2 (1), 50-62, 2014 | 118 | 2014 |
| New security threats against chips containing scan chain structures J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre 2011 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2011 | 87 | 2011 |
| A watchdog processor to detect data and control flow errors A Benso, S Di Carlo, G Di Natale, P Prinetto 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 144-148, 2003 | 87 | 2003 |
| Are advanced DfT structures sufficient for preventing scan-attacks? J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre 2012 IEEE 30th VLSI Test Symposium (VTS), 246-251, 2012 | 85 | 2012 |
| A novel differential scan attack on advanced DFT structures JD Rolt, GD Natale, ML Flottes, B Rouzeyre ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4 …, 2013 | 76 | 2013 |
| Lifting: A flexible open-source fault simulator A Bosio, G Di Natale 2008 17th Asian Test Symposium, 35-40, 2008 | 71 | 2008 |
| Scan attacks and countermeasures in presence of scan response compactors J DaRolt, G Di Natale, ML Flottes, B Rouzeyre 2011 Sixteenth IEEE European Test Symposium, 19-24, 2011 | 69 | 2011 |
| An on-line BIST RAM architecture with self-repair capabilities A Benso, S Chiusano, G Di Natale, P Prinetto IEEE Transactions on Reliability 51 (1), 123-128, 2002 | 69 | 2002 |
| Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model JM Dutertre, V Beroulle, P Candelier, S De Castro, LB Faber, ML Flottes, ... 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 1-6, 2018 | 66 | 2018 |
| Hardware security and trust N Sklavos, R Chaves, G Di Natale, F Regazzoni Cham, Switzerland: Springer, 2017 | 66 | 2017 |
| Control-flow checking via regular expressions A Benso, S Di Carlo, G Di Natale, P Prinetto, L Tagliaferri Proceedings 10th Asian Test Symposium, 299-303, 2001 | 65 | 2001 |
| Preventing scan attacks on secure circuits through scan chain encryption M Da Silva, ML Flottes, G Di Natale, B Rouzeyre IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 64 | 2018 |
| STT-MRAM-based PUF architecture exploiting magnetic tunnel junction fabrication-induced variability EI Vatajelu, GD Natale, M Barbareschi, L Torres, M Indaco, P Prinetto ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (1), 1-21, 2016 | 64 | 2016 |
| Secure JTAG implementation using Schnorr protocol A Das, J Da Rolt, S Ghosh, S Seys, S Dupuis, G Di Natale, ML Flottes, ... Journal of Electronic Testing 29, 193-209, 2013 | 55 | 2013 |
| A reliable architecture for parallel implementations of the advanced encryption standard G Di Natale, M Doulcier, ML Flottes, B Rouzeyre Journal of Electronic Testing 25 (4), 269-278, 2009 | 54 | 2009 |
| Self-test techniques for crypto-devices G Di Natale, M Doulcier, ML Flottes, B Rouzeyre IEEE transactions on very large scale integration (VLSI) systems 18 (2), 329-333, 2009 | 52 | 2009 |
| March AB, March AB1: new March tests for unlinked dynamic memory faults A Benso, A Bosio, S Di Carlo, G Di Natale, P Prinetto IEEE International Conference on Test, 2005., 8 pp.-841, 2005 | 51 | 2005 |
| A programmable BIST architecture for clusters of multiple-port SRAMs A Benso, S Di Carlo, G Di Natale, P Prinetto, ML Bodoni Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000 | 50 | 2000 |
Marie-Lise FlottesLIRMMכתובת אימייל מאומתת בדומיין lirmm.fr