| Integer programming based topology selection of cell-level analog circuits PC Maulik, LR Carley, RA Rutenbar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995 | 123 | 1995 |
| Efficient and scalable FIR filter architecture for decimation PC Maulik, CS Mandeep, Z Kan US Patent 6,260,053, 2001 | 106 | 2001 |
| A 16-bit 250-kHz delta-sigma modulator and decimation filter PC Maulik, MS Chadha, WL Lee, PJ Crawley IEEE Journal of solid-state circuits 35 (4), 458-467, 2000 | 94 | 2000 |
| Sizing of cell-level analog circuits using constrained optimization techniques PC Maulik, LR Carley, DJ Allstot IEEE Journal of Solid-State Circuits 28 (3), 233-241, 1993 | 84 | 1993 |
| A DLL-Based Programmable Clock Multiplier in 0.18-m CMOS With70 dBc Reference Spur PC Maulik, DA Mercer IEEE Journal of Solid-State Circuits 42 (8), 1642-1648, 2007 | 69 | 2007 |
| A mixed-integer nonlinear programming approach to analog circuit synthesis PC Maulik, LR Carley, RA Rutenbar [1992] Proceedings 29th ACM/IEEE Design Automation Conference, 698-703, 1992 | 60 | 1992 |
| Automating analog circuit design using constrained optimization techniques PC Maulik, LR Carley 1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991 | 51 | 1991 |
| Applications and Algorithm Partitioning on Warp. M Annaratone, FJ Bitz, E Clune, HT Kung, PC Maulik, HB Ribas, ... COMPCON, 272-279, 1987 | 33 | 1987 |
| Applications experience on Warp M Annaratone, F Bitz, J Deutch, L Hamey, HT Kung, P Maulik, H Ribas, ... Proceedings of the 1987 National Computer Conference, 149-158, 1987 | 29 | 1987 |
| Input sampling structure for delta-sigma modulator PC Maulik, PJ Crawley US Patent 6,147,631, 2000 | 25 | 2000 |
| Accurate gain calibration of analog to digital converters PC Maulik, MS Chadha US Patent 6,111,529, 2000 | 20 | 2000 |
| Methods and apparatus for calibration of automatic gain control in broadcast tuners PC Maulik, S Rose, D Paterson, H L'bahy, N Abaskharoun US Patent 7,853,229, 2010 | 19 | 2010 |
| Metastability error reduction in asynchronous successive approximation analog to digital converter P Maulik, N Govind US Patent 9,621,179, 2017 | 18 | 2017 |
| Frequency tuning of wide temperature range CMOS LC VCOs PC Maulik, PW Lai IEEE journal of solid-state circuits 46 (9), 2033-2040, 2011 | 18 | 2011 |
| An analog/digital interface for cellular telephony PC Maulik, N van Bavel, KS Albright, XM Gong IEEE journal of solid-state circuits 30 (3), 201-209, 1995 | 18 | 1995 |
| A 12-bit integrated analog front end for broadband wireline networks I Mehr, PC Maulik, D Paterson IEEE Journal of Solid-State Circuits 37 (3), 302-309, 2002 | 16 | 2002 |
| Rapid redesign of analog standard cells using constrained optimization techniques PC Maulik, MJ Flynn, DJ Allstot, LR Carley 1992 Proceedings of the IEEE Custom Integrated Circuits Conference, 8.1. 1-8 …, 1992 | 16 | 1992 |
| Robust start-up circuit for CMOS bandgap reference PC Maulik US Patent 6,133,719, 2000 | 15 | 2000 |
| Frequency compensation for single-ended class AB operational amplifiers with fully-differential input stages PC Maulik US Patent 6,281,751, 2001 | 12 | 2001 |
| Gain calibration by applying a portion of an input voltage to voltage associated with a capacitor array P Maulik, N Govind US Patent 9,602,119, 2017 | 10 | 2017 |
