| Reduced overhead gate level logic encryption K Juretus, I Savidis Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 15-20, 2016 | 43 | 2016 |
| Lightweight hardware implementation of binary ring-LWE PQC accelerator BJ Lucas, A Alwan, M Murzello, Y Tu, P He, AJ Schwartz, D Guevara, ... IEEE Computer Architecture Letters 21 (1), 17-20, 2022 | 34 | 2022 |
| Reducing logic encryption overhead through gate level key insertion K Juretus, I Savidis 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1714-1717, 2016 | 31 | 2016 |
| Time domain sequential locking for increased security K Juretus, I Savidis 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 20 | 2018 |
| Securing analog mixed-signal integrated circuits through shared dependencies K Juretus, V Venugopal Rao, I Savidis Proceedings of the 2019 Great Lakes Symposium on VLSI, 483-488, 2019 | 19 | 2019 |
| Synthesis of hidden state transitions for sequential logic locking K Juretus, I Savidis IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 17 | 2020 |
| Increasing the SAT attack resiliency of in-cone logic locking K Juretus, I Savidis 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 17 | 2019 |
| Physical layer encryption for wireless OFDM communication systems M Jacovic, K Juretus, N Kandasamy, I Savidis, KR Dandekar Journal of Hardware and Systems Security 4 (3), 230-245, 2020 | 15 | 2020 |
| Increased output corruption and structural attack resilience for SAT attack secure logic locking K Juretus, I Savidis IEEE transactions on computer-aided design of integrated circuits and …, 2020 | 15 | 2020 |
| Security vulnerabilities of obfuscated analog circuits VV Rao, K Juretus, I Savidis 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 13 | 2020 |
| Physical gate based preamble obfuscation for securing wireless communication J Chacko, K Juretus, M Jacovic, C Sahin, N Kandasamy, I Savidis, ... 2017 International Conference on Computing, Networking and Communications …, 2017 | 12 | 2017 |
| Characterization of in-cone logic locking resiliency against the SAT attack K Juretus, I Savidis IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 11 | 2019 |
| Importance of multi-parameter SAT attack exploration for integrated circuit security K Juretus, I Savidis 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 366-369, 2018 | 11 | 2018 |
| Sparse array design for optimum beamforming using deep learning SA Hamza, K Juretus, MG Amin Sparse Arrays for Radar, Sonar, and Communications, 215-250, 2024 | 9 | 2024 |
| Deep learning sparse array design using binary switching configurations SA Hamza, K Juretus, MG Amin, F Ahmad ICASSP 2023-2023 IEEE International Conference on Acoustics, Speech and …, 2023 | 8 | 2023 |
| Hidden costs of analog deobfuscation attacks VV Rao, K Juretus, I Savidis IEEE transactions on very large scale integration (VLSI) systems 31 (11 …, 2023 | 4 | 2023 |
| Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures D Werner, K Juretus, I Savidis, M Hempstead 2018 IEEE 36th International Conference on Computer Design (ICCD), 83-91, 2018 | 4 | 2018 |
| Enhanced circuit security through hidden state transitions K Juretus, I Savidis Government Microcircuit Applications & Critical Technology Conference …, 2018 | 4 | 2018 |
| Reduced overhead gate level logic encryption I Savidis, K Juretus US Patent 11,282,414, 2022 | 3 | 2022 |
| Reducing logic locking key leakage through the scan chain K Juretus, I Savidis 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 3 | 2020 |
Ioannis SavidisAssociate Professor, Drexel Universityכתובת אימייל מאומתת בדומיין coe.drexel.edu
