| MOMENT: A cross-layer method to mitigate multiple event transients in combinational circuits AM Hajisadeghi, H Bardareh, HR Zarandi 2018 21st Euromicro Conference on Digital System Design (DSD), 237-243, 2018 | 10 | 2018 |
| DUSTER: Dual source write termination method for STT-RAM memories SS Faraji, J Talafy, AM Hajisadeghi, HR Zarandi 2018 21st Euromicro Conference on Digital System Design (DSD), 182-189, 2018 | 8 | 2018 |
| A low-cost soft error tolerant read circuit for single/multi-level cross-point RRAM arrays H Bardareh, AM Hajisadeghi, HR Zarandi 2018 IEEE 24th International Symposium on On-Line Testing And Robust System …, 2018 | 8 | 2018 |
| DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories S Seyedfaraji, AM Hajisadeghi, J Talafy, HR Zarandi Microprocessors and Microsystems 73, 102963, 2020 | 7 | 2020 |
| TAMPER: Thermal assistant method to improve write performance in STT-RAM memories SS Faraji, AM Hajisadeghi, H Zarandi 2019 27th Iranian Conference on Electrical Engineering (ICEE), 2039-2044, 2019 | 5 | 2019 |
| A fast and efficient fault tree analysis using approximate computing S Hashemi, AM Hajisadeghi, HR Zarandi, S Pourmozafari 2019 15th European Dependable Computing Conference (EDCC), 39-46, 2019 | 4 | 2019 |
| Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM AM Hajisadeghi, M Momtazpour, HR Zarandi Future Generation Computer Systems 160, 40-53, 2024 | 2 | 2024 |
| EARL: an efficient approximate hardware framework for accelerating fault tree analysis S Hashemi, AM Hajisadeghi, HR Zarandi 2022 25th Euromicro Conference on Digital System Design (DSD), 32-38, 2022 | 2 | 2022 |
| CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics AM Hajisadeghi, HR Zarandi Microprocessors and Microsystems, 104282, 2021 | 2 | 2021 |
| Stoch-IMC: A bit-parallel stochastic in-memory computing architecture based on STT-MRAM AM Hajisadeghi, HR Zarandi, M Momtazpour AEU-International Journal of Electronics and Communications 190, 155614, 2025 | | 2025 |
| Combinational Standard Cells Adjacency Effect Analysis on Soft Error Occurrence Using Device-Level Simulations A Zarei, AM Hajisadeghi, HR Zarandi 2024 5th CPSSI International Symposium on Cyber-Physical Systems …, 2024 | | 2024 |
| ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks A Sedaghatgoo, AM Hajisadeghi, M Momtazpour, N Bagherzadeh arXiv preprint arXiv:2402.04431, 2024 | | 2024 |
| Nanoscale memristive devices: Threats and solutions AM Hajisadeghi, J Talafy, HR Zarandi Nanoscale Memristor Device and Circuits Design, 137-163, 2024 | | 2024 |
| The Detector of Water Leakage in Metal Pipes using the Noise Correlation Method Morteza Saheb Zamani, Ali Samadzadeh, Amir M. Hajisadeghi, Azim Farghadan ... Iran Patent, 2022 | | 2022 |
| Bit Error Mitigation Using Unequal Resistivity Levels in Memristors AM Hajisadeghi, P Pourmomen, HR Zarandi 2022 30th International Conference on Electrical Engineering (ICEE), 300-304, 2022 | | 2022 |
| Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method AM Hajisadeghi, HR Zarandi, SH JALILIAN NASHRIYYAH-I MUHANDISI-I BARQ VA MUHANDISI-I KAMPYUTAR-I IRAN, B-MUHANDISI-I …, 2021 | | 2021 |
| Parallelization of the Ant Colony Optimization for The Shortest Path Problem using OpenMP and MPI AM Hajisadeghi, M Afrad International Conference on Knowledge-based Research in Computer Engineering …, 2017 | | 2017 |
Hamid R. ZarandiAssociate Professor, Department of Computer Engineering, Amirkabir University of Technologyכתובת אימייל מאומתת בדומיין aut.ac.ir