| Can recursive bisection alone produce routable placements? AE Caldwell, AB Kahng, IL Markov Proceedings of the 37th annual design automation conference, 477-482, 2000 | 506 | 2000 |
| Improved algorithms for hypergraph bipartitioning AE Caldwell, AB Kahng, IL Markov Proceedings of the 2000 Asia and South Pacific Design Automation Conference …, 2000 | 208 | 2000 |
| Optimal partitioners and end-case placers for standard-cell layout AE Caldwell, AB Kahng, IL Markov Proceedings of the 1999 international symposium on physical design, 90-96, 1999 | 187 | 1999 |
| On wirelength estimations for row-based placement AE Caldwell, AB Kahng, S Mantik, IL Markov, A Zelikovsky Proceedings of the 1998 international symposium on Physical design, 4-11, 1998 | 167 | 1998 |
| Effective iterative techniques for fingerprinting design IP AE Caldwell, HJ Choi, AB Kahng, S Mantik, M Potkonjak, G Qu, JL Wong Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 843-848, 1999 | 151 | 1999 |
| Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction S Teig, A Caldwell US Patent 6,526,555, 2003 | 82 | 2003 |
| Method and apparatus for decomposing functions in a configurable IC A Caldwell, H Schmit, S Teig US Patent 7,530,033, 2009 | 71 | 2009 |
| Operational time extension A Rohe, S Teig, H Schmit, J Redgrave, A Caldwell US Patent 7,236,009, 2007 | 66 | 2007 |
| Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits S Teig, A Caldwell US Patent 6,711,727, 2004 | 65 | 2004 |
| Design and implementation of move-based heuristics for VLSI hypergraph partitioning AE Caldwell, AB Kahng, IL Markov Journal of Experimental Algorithmics (JEA) 5, 5-es, 2000 | 64 | 2000 |
| Routing method and apparatus S Teig, O Buset, E Jacques, A Caldwell, J Frankle US Patent 7,155,697, 2006 | 61 | 2006 |
| GTX: The MARCO GSRC technology extrapolation system AE Caldwell, Y Cao, AB Kahng, F Koushanfar, H Lu, IL Markov, M Oliver, ... Proceedings of the 37th Annual Design Automation Conference, 693-698, 2000 | 59 | 2000 |
| Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting AE Caldwell, AB Kahng, AA Kennings, IL Markov Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 349-354, 1999 | 59 | 1999 |
| Method and apparatus for routing with independent goals on different layers J Frankle, A Caldwell US Patent 7,480,885, 2009 | 52 | 2009 |
| Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources DJ Pugh, A Caldwell US Patent 7,372,297, 2008 | 48 | 2008 |
| Hierarchical whitespace allocation in top-down placement AE Caldwell, AB Kahng, IL Markov IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003 | 48 | 2003 |
| Toward CAD-IP reuse: The MARCO GSRC bookshelf of fundamental CAD algorithms AE Caldwell, AB Kahng, IL Markov IEEE Design and Test 19 (3), 70-79, 2002 | 43 | 2002 |
| Configurable storage elements M Voogel, S Teig, TS Chanack, A Caldwell, J Ko, T Chandler US Patent 8,760,193, 2014 | 42 | 2014 |
| Translating a user design in a configurable IC for debugging the user design B Hutchings, A Caldwell, S Teig US Patent 8,069,425, 2011 | 39 | 2011 |
| Method and apparatus for decomposing functions in a configurable IC A Caldwell, H Schmit, S Teig US Patent 8,726,213, 2014 | 37 | 2014 |
